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Preserve operand flags in convertToThreeAddress() by copying operands.
No test case, this is a generalization of r160260. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162485 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
c1f10fd5b9
commit
91f3a6cfd9
@ -1786,10 +1786,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineInstr *MI = MBBI;
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MachineFunction &MF = *MI->getParent()->getParent();
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// All instructions input are two-addr instructions. Get the known operands.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isKill = MI->getOperand(1).isKill();
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const MachineOperand &Dest = MI->getOperand(0);
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const MachineOperand &Src = MI->getOperand(1);
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MachineInstr *NewMI = NULL;
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// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
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@ -1807,11 +1805,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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if (B != C) return 0;
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unsigned A = MI->getOperand(0).getReg();
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unsigned M = MI->getOperand(3).getImm();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
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.addReg(A, RegState::Define | getDeadRegState(isDead))
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.addReg(B, getKillRegState(isKill)).addImm(M);
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.addOperand(Dest).addOperand(Src).addImm(M);
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break;
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}
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case X86::SHUFPDrri: {
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@ -1821,15 +1817,13 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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if (B != C) return 0;
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unsigned A = MI->getOperand(0).getReg();
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unsigned M = MI->getOperand(3).getImm();
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// Convert to PSHUFD mask.
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M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
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.addReg(A, RegState::Define | getDeadRegState(isDead))
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.addReg(B, getKillRegState(isKill)).addImm(M);
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.addOperand(Dest).addOperand(Src).addImm(M);
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break;
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}
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case X86::SHL64ri: {
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@ -1840,15 +1834,14 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (ShAmt == 0 || ShAmt >= 4) return 0;
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// LEA can't handle RSP.
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if (TargetRegisterInfo::isVirtualRegister(Src) &&
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!MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
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if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
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!MF.getRegInfo().constrainRegClass(Src.getReg(),
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&X86::GR64_NOSPRegClass))
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return 0;
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addReg(Dest, RegState::Define | getDeadRegState(isDead))
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.addReg(0).addImm(1 << ShAmt)
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.addReg(Src, getKillRegState(isKill))
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.addImm(0).addReg(0);
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.addOperand(Dest)
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.addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
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break;
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}
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case X86::SHL32ri: {
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@ -1859,15 +1852,15 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (ShAmt == 0 || ShAmt >= 4) return 0;
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// LEA can't handle ESP.
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if (TargetRegisterInfo::isVirtualRegister(Src) &&
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!MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
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if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
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!MF.getRegInfo().constrainRegClass(Src.getReg(),
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&X86::GR32_NOSPRegClass))
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return 0;
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addReg(Dest, RegState::Define | getDeadRegState(isDead))
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.addReg(0).addImm(1 << ShAmt)
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.addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
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.addOperand(Dest)
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.addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
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break;
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}
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case X86::SHL16ri: {
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@ -1880,10 +1873,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addReg(Dest, RegState::Define | getDeadRegState(isDead))
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.addReg(0).addImm(1 << ShAmt)
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.addReg(Src, getKillRegState(isKill))
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.addImm(0).addReg(0);
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.addOperand(Dest)
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.addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
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break;
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}
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default: {
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@ -1906,14 +1897,12 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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(const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
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// LEA can't handle RSP.
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if (TargetRegisterInfo::isVirtualRegister(Src) &&
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!MF.getRegInfo().constrainRegClass(Src, RC))
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if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
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!MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
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return 0;
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, 1);
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest).addOperand(Src), 1);
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break;
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}
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case X86::INC16r:
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@ -1921,10 +1910,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, 1);
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), 1);
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break;
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case X86::DEC64r:
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case X86::DEC32r:
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@ -1936,14 +1923,12 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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(const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
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(const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
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// LEA can't handle RSP.
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if (TargetRegisterInfo::isVirtualRegister(Src) &&
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!MF.getRegInfo().constrainRegClass(Src, RC))
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if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
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!MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
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return 0;
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, -1);
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest).addOperand(Src), -1);
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break;
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}
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case X86::DEC16r:
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@ -1951,10 +1936,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, -1);
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src), -1);
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break;
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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@ -1981,9 +1964,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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return 0;
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NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, Src2, isKill2);
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.addOperand(Dest),
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Src.getReg(), Src.isKill(), Src2, isKill2);
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// Preserve undefness of the operands.
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bool isUndef = MI->getOperand(1).isUndef();
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@ -2003,9 +1985,15 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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unsigned Src2 = MI->getOperand(2).getReg();
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bool isKill2 = MI->getOperand(2).isKill();
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NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, Src2, isKill2);
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.addOperand(Dest),
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Src.getReg(), Src.isKill(), Src2, isKill2);
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// Preserve undefness of the operands.
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bool isUndef = MI->getOperand(1).isUndef();
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bool isUndef2 = MI->getOperand(2).isUndef();
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NewMI->getOperand(1).setIsUndef(isUndef);
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NewMI->getOperand(3).setIsUndef(isUndef2);
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if (LV && isKill2)
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LV->replaceKillInstruction(Src2, MI, NewMI);
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break;
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@ -2015,10 +2003,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, MI->getOperand(2).getImm());
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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case X86::ADD32ri:
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case X86::ADD32ri8:
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@ -2026,10 +2013,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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case X86::ADD32ri8_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, MI->getOperand(2).getImm());
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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}
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case X86::ADD16ri:
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@ -2039,10 +2025,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addReg(Dest, RegState::Define |
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getDeadRegState(isDead)),
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Src, isKill, MI->getOperand(2).getImm());
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NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
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.addOperand(Dest).addOperand(Src),
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MI->getOperand(2).getImm());
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break;
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}
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}
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@ -2051,10 +2036,10 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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if (!NewMI) return 0;
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if (LV) { // Update live variables
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if (isKill)
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LV->replaceKillInstruction(Src, MI, NewMI);
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if (isDead)
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LV->replaceKillInstruction(Dest, MI, NewMI);
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if (Src.isKill())
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LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
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if (Dest.isDead())
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LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
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}
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MFI->insert(MBBI, NewMI); // Insert the new inst
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