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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239672 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2015-06-13 12:51:39 +00:00
parent 8e2ed1643a
commit 9223c2cb1e
1 changed files with 6 additions and 6 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -6356,7 +6356,7 @@ static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
/// ///
/// This helper function produces an 8-bit shuffle immediate corresponding to /// This helper function produces an 8-bit shuffle immediate corresponding to
/// the ubiquitous shuffle encoding scheme used in x86 instructions for /// the ubiquitous shuffle encoding scheme used in x86 instructions for
/// shuffling 8 lanes. /// shuffling 8 lanes.
static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL, static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
SelectionDAG &DAG) { SelectionDAG &DAG) {
assert(Mask.size() <= 8 && assert(Mask.size() <= 8 &&
@ -13021,11 +13021,11 @@ SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
RecipOp = "vec-sqrtf"; RecipOp = "vec-sqrtf";
else else
return SDValue(); return SDValue();
TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
if (!Recips.isEnabled(RecipOp)) if (!Recips.isEnabled(RecipOp))
return SDValue(); return SDValue();
RefinementSteps = Recips.getRefinementSteps(RecipOp); RefinementSteps = Recips.getRefinementSteps(RecipOp);
UseOneConstNR = false; UseOneConstNR = false;
return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
@ -13038,7 +13038,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
unsigned &RefinementSteps) const { unsigned &RefinementSteps) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
const char *RecipOp; const char *RecipOp;
// SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps. // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
// TODO: Add support for AVX512 (v16f32). // TODO: Add support for AVX512 (v16f32).
// It is likely not profitable to do this for f64 because a double-precision // It is likely not profitable to do this for f64 because a double-precision
@ -13053,7 +13053,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
RecipOp = "vec-divf"; RecipOp = "vec-divf";
else else
return SDValue(); return SDValue();
TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
if (!Recips.isEnabled(RecipOp)) if (!Recips.isEnabled(RecipOp))
return SDValue(); return SDValue();
@ -15110,7 +15110,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
if (IntrWithRoundingModeOpcode != 0) { if (IntrWithRoundingModeOpcode != 0) {
unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue(); unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode, return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
dl, Op.getValueType(), Src, RoundingMode), dl, Op.getValueType(), Src, RoundingMode),
Mask, PassThru, Subtarget, DAG); Mask, PassThru, Subtarget, DAG);