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[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2013-11-29 01:29:16 +00:00
parent e9f8ce8cde
commit 9224192321
3 changed files with 90 additions and 35 deletions
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2
lib/Target/AArch64/AArch64InstrNEON.td
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@ -7818,6 +7818,7 @@ defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>; defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> { multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
let DecoderMethod = "DecodeSHLLInstruction" in {
def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode, def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
(outs VPR128:$Rd), (outs VPR128:$Rd),
(ins VPR64:$Rn, uimm_exact8:$Imm), (ins VPR64:$Rn, uimm_exact8:$Imm),
@ -7854,6 +7855,7 @@ multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
asmop # "2\t$Rd.2d, $Rn.4s, $Imm", asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
[], NoItinerary>; [], NoItinerary>;
} }
}
defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>; defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;

36
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@ -238,6 +238,10 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static bool Check(DecodeStatus &Out, DecodeStatus In); static bool Check(DecodeStatus &Out, DecodeStatus In);
#include "AArch64GenDisassemblerTables.inc" #include "AArch64GenDisassemblerTables.inc"
@ -1534,3 +1538,35 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned size = fieldFromInstruction(Insn, 22, 2);
unsigned Q = fieldFromInstruction(Insn, 30, 1);
DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
if(Q)
DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
else
DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
switch (size) {
case 0:
Inst.addOperand(MCOperand::CreateImm(8));
break;
case 1:
Inst.addOperand(MCOperand::CreateImm(16));
break;
case 2:
Inst.addOperand(MCOperand::CreateImm(32));
break;
default :
return MCDisassembler::Fail;
}
return MCDisassembler::Success;
}

17
test/MC/Disassembler/AArch64/neon-instructions.txt
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@ -674,6 +674,23 @@
0xf5 0xdd 0x23 0x4e 0xf5 0xdd 0x23 0x4e
0xab 0xdc 0x77 0x4e 0xab 0xdc 0x77 0x4e
#----------------------------------------------------------------------
# Vector Shift Left long
#----------------------------------------------------------------------
# CHECK: shll2 v2.8h, v4.16b, #8
# CHECK: shll2 v6.4s, v8.8h, #16
# CHECK: shll2 v6.2d, v8.4s, #32
# CHECK: shll v2.8h, v4.8b, #8
# CHECK: shll v6.4s, v8.4h, #16
# CHECK: shll v6.2d, v8.2s, #32
0x82,0x38,0x21,0x6e
0x06,0x39,0x61,0x6e
0x06,0x39,0xa1,0x6e
0x82,0x38,0x21,0x2e
0x06,0x39,0x61,0x2e
0x06,0x39,0xa1,0x2e
#---------------------------------------------------------------------- #----------------------------------------------------------------------
# Vector Shift Left by Immediate # Vector Shift Left by Immediate
#---------------------------------------------------------------------- #----------------------------------------------------------------------