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[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7818,41 +7818,43 @@ defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
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defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
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defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
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multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
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multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
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def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
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let DecoderMethod = "DecodeSHLLInstruction" in {
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(outs VPR128:$Rd),
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def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
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(ins VPR64:$Rn, uimm_exact8:$Imm),
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(outs VPR128:$Rd),
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asmop # "\t$Rd.8h, $Rn.8b, $Imm",
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(ins VPR64:$Rn, uimm_exact8:$Imm),
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[], NoItinerary>;
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asmop # "\t$Rd.8h, $Rn.8b, $Imm",
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[], NoItinerary>;
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def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
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(outs VPR128:$Rd),
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def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
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(ins VPR64:$Rn, uimm_exact16:$Imm),
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(outs VPR128:$Rd),
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asmop # "\t$Rd.4s, $Rn.4h, $Imm",
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(ins VPR64:$Rn, uimm_exact16:$Imm),
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[], NoItinerary>;
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asmop # "\t$Rd.4s, $Rn.4h, $Imm",
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[], NoItinerary>;
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def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
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(outs VPR128:$Rd),
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def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
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(ins VPR64:$Rn, uimm_exact32:$Imm),
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(outs VPR128:$Rd),
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asmop # "\t$Rd.2d, $Rn.2s, $Imm",
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(ins VPR64:$Rn, uimm_exact32:$Imm),
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[], NoItinerary>;
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asmop # "\t$Rd.2d, $Rn.2s, $Imm",
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[], NoItinerary>;
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def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
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(outs VPR128:$Rd),
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def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
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(ins VPR128:$Rn, uimm_exact8:$Imm),
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(outs VPR128:$Rd),
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asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
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(ins VPR128:$Rn, uimm_exact8:$Imm),
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[], NoItinerary>;
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asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
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[], NoItinerary>;
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def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
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(outs VPR128:$Rd),
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def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
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(ins VPR128:$Rn, uimm_exact16:$Imm),
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(outs VPR128:$Rd),
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asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
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(ins VPR128:$Rn, uimm_exact16:$Imm),
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[], NoItinerary>;
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asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
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[], NoItinerary>;
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def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
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(outs VPR128:$Rd),
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def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
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(ins VPR128:$Rn, uimm_exact32:$Imm),
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(outs VPR128:$Rd),
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asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
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(ins VPR128:$Rn, uimm_exact32:$Imm),
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[], NoItinerary>;
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asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
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[], NoItinerary>;
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}
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}
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}
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defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
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defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
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@ -238,6 +238,10 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder);
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const void *Decoder);
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static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static bool Check(DecodeStatus &Out, DecodeStatus In);
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static bool Check(DecodeStatus &Out, DecodeStatus In);
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#include "AArch64GenDisassemblerTables.inc"
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#include "AArch64GenDisassemblerTables.inc"
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@ -1534,3 +1538,35 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 0, 5);
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unsigned Rn = fieldFromInstruction(Insn, 5, 5);
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unsigned size = fieldFromInstruction(Insn, 22, 2);
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unsigned Q = fieldFromInstruction(Insn, 30, 1);
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DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
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if(Q)
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DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
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else
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DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
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switch (size) {
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case 0:
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Inst.addOperand(MCOperand::CreateImm(8));
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break;
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case 1:
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Inst.addOperand(MCOperand::CreateImm(16));
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break;
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case 2:
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Inst.addOperand(MCOperand::CreateImm(32));
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break;
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default :
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return MCDisassembler::Fail;
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}
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return MCDisassembler::Success;
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}
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@ -674,6 +674,23 @@
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0xf5 0xdd 0x23 0x4e
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0xf5 0xdd 0x23 0x4e
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0xab 0xdc 0x77 0x4e
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0xab 0xdc 0x77 0x4e
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#----------------------------------------------------------------------
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# Vector Shift Left long
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#----------------------------------------------------------------------
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# CHECK: shll2 v2.8h, v4.16b, #8
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# CHECK: shll2 v6.4s, v8.8h, #16
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# CHECK: shll2 v6.2d, v8.4s, #32
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# CHECK: shll v2.8h, v4.8b, #8
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# CHECK: shll v6.4s, v8.4h, #16
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# CHECK: shll v6.2d, v8.2s, #32
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0x82,0x38,0x21,0x6e
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0x06,0x39,0x61,0x6e
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0x06,0x39,0xa1,0x6e
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0x82,0x38,0x21,0x2e
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0x06,0x39,0x61,0x2e
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0x06,0x39,0xa1,0x2e
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#----------------------------------------------------------------------
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#----------------------------------------------------------------------
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# Vector Shift Left by Immediate
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# Vector Shift Left by Immediate
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#----------------------------------------------------------------------
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#----------------------------------------------------------------------
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