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Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142485 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2011-10-19 09:24:02 +00:00
parent b677a135ac
commit 922ad78776
1 changed files with 27 additions and 5 deletions
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32
lib/Target/ARM/ARMISelLowering.cpp
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@@ -5820,10 +5820,14 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
.addImm(NumLPads)); .addImm(NumLPads));
} else { } else {
MachineConstantPool *ConstantPool = MF->getConstantPool(); MachineConstantPool *ConstantPool = MF->getConstantPool();
const Constant *C = Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
ConstantInt::get(Type::getInt32Ty(MF->getFunction()->getContext()), const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
NumLPads);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); // MachineConstantPool wants an explicit alignment.
unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
if (Align == 0)
Align = getTargetData()->getTypeAllocSize(C->getType());
unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
unsigned VReg1 = MRI->createVirtualRegister(TRC); unsigned VReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci)) AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
@@ -5887,7 +5891,7 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
.addReg(NewVReg1) .addReg(NewVReg1)
.addImm(NumLPads)); .addImm(NumLPads));
} else { } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
unsigned VReg1 = MRI->createVirtualRegister(TRC); unsigned VReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
.addImm(NumLPads & 0xFFFF)); .addImm(NumLPads & 0xFFFF));
@@ -5903,6 +5907,24 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
.addReg(NewVReg1) .addReg(NewVReg1)
.addReg(VReg2)); .addReg(VReg2));
} else {
MachineConstantPool *ConstantPool = MF->getConstantPool();
Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
// MachineConstantPool wants an explicit alignment.
unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
if (Align == 0)
Align = getTargetData()->getTypeAllocSize(C->getType());
unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
unsigned VReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
.addReg(VReg1, RegState::Define)
.addConstantPoolIndex(Idx));
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
.addReg(NewVReg1)
.addReg(VReg1, RegState::Kill));
} }
BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))