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Fix some incorrectly named u10 / lu10 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173090 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-21 21:12:30 +00:00
parent 3c8da314f1
commit 923cc3ebb0
1 changed files with 11 additions and 24 deletions
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27
lib/Target/XCore/XCoreInstrInfo.td
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@ -649,36 +649,23 @@ defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
// TODO ldwcpl, blacp
let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
def LDAP_u10 : _FU10<
(outs),
(ins i32imm:$addr),
"ldap r11, $addr",
[]>;
def LDAPF_u10 : _FU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", []>;
let Defs = [R11], isReMaterializable = 1 in
def LDAP_lu10 : _FLU10<
(outs),
(ins i32imm:$addr),
"ldap r11, $addr",
def LDAPF_lu10 : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr",
[(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
let Defs = [R11], isReMaterializable = 1 in
def LDAP_lu10_ba : _FLU10<(outs),
(ins i32imm:$addr),
"ldap r11, $addr",
def LDAPF_lu10_ba : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr",
[(set R11, (pcrelwrapper tblockaddress:$addr))]>;
let isCall=1,
// All calls clobber the link register and the non-callee-saved registers:
Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
def BL_u10 : _FU10<
(outs), (ins calltarget:$target),
"bl $target",
def BLRF_u10 : _FU10<(outs), (ins calltarget:$target), "bl $target",
[(XCoreBranchLink immU10:$target)]>;
def BL_lu10 : _FLU10<
(outs), (ins calltarget:$target),
"bl $target",
def BLRF_lu10 : _FLU10<(outs), (ins calltarget:$target), "bl $target",
[(XCoreBranchLink immU20:$target)]>;
}
@ -979,8 +966,8 @@ def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
/// sext_inreg
def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;