6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-06 05:06:45 +00:00
Code Issues Projects Releases Wiki Activity

MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to

Browse Source 
avoid same prefix byte problem as in r104062.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-05-19 04:31:36 +00:00
parent ea420b20d4
commit 9248b3208a
1 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
View File

@ -329,18 +329,20 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
// CALL64pcrel32 - This instruction has register inputs modeled as normal
// uses instead of implicit uses. As such, truncate off all but the first
// operand (the callee). FIXME: Change isel.
// CALL64r, CALL64pcrel32 - These instructions have register inputs modeled as
// normal uses instead of implicit uses. As such, truncate off all but the
// first operand (the callee). FIXME: Change isel.
case X86::CALL64r:
case X86::CALL64pcrel32: {
unsigned Opcode = OutMI.getOpcode();
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(X86::CALL64pcrel32);
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
// The assembler backend wants to see branches in their small form and relax
// them to their large form. The JIT can only handle the large form because
// it does not do relaxation. For now, translate the large form to the