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R600/SI: Add 32-bit encoding of v_cndmask_b32

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This was done by refactoring the v_cndmask_b32 tablegen definition
to use inherit from VOP2Inst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-03-10 16:16:44 +00:00
parent 137e1f3f28
commit 92811fa2c7
3 changed files with 25 additions and 6 deletions
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5
lib/Target/R600/SIInstrInfo.td
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@ -802,6 +802,11 @@ def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
let Asm64 = " $dst, $src0, $src1, $src2";
}
def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {

21
lib/Target/R600/SIInstructions.td
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@ -1483,13 +1483,17 @@ defm V_INTERP_MOV_F32 : VINTRP_m <
// VOP2 Instructions
//===----------------------------------------------------------------------===//
defm V_CNDMASK_B32_e64 : VOP3_m_nomods <vop3<0x100>, (outs VGPR_32:$dst),
(ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
"v_cndmask_b32_e64 $dst, $src0, $src1, $src2",
[(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))],
"v_cndmask_b32_e64", 3
>;
multiclass V_CNDMASK <vop2 op, string name> {
defm _e32 : VOP2_m <
op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins32, VOP_CNDMASK.Asm32, [],
name, name>;
defm _e64 : VOP3_m <
op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64,
name#"_e64"#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3>;
}
defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">;
let isCommutable = 1 in {
defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
@ -2261,6 +2265,11 @@ def : Pat <
(V_BCNT_U32_B32_e64 $popcnt, $val)
>;
def : Pat <
(i32 (select i1:$src0, i32:$src1, i32:$src2)),
(V_CNDMASK_B32_e64 $src2, $src1, $src0)
>;
/********** ======================= **********/
/********** Image sampling patterns **********/
/********** ======================= **********/

5
lib/Target/R600/SIShrinkInstructions.cpp
View File

@ -88,6 +88,11 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
// Can't shrink instruction with three operands.
// FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
// a special case for it. It can only be shrunk if the third operand
// is vcc. We should handle this the same way we handle vopc, by addding
// a register allocation hint pre-regalloc and then do the shrining
// post-regalloc.
if (Src2)
return false;