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R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation. Test is disabled for VI since there seems to be a problem with one of the buffer load instructions on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
f1b6c1f287
commit
9295d69bea
@ -907,10 +907,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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}
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case Intrinsic::AMDGPU_div_fmas:
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// FIXME: Dropping bool parameter. Work is needed to support the implicit
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// read from VCC.
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return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
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Op.getOperand(4));
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case Intrinsic::AMDGPU_div_fixup:
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return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
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@ -35,6 +35,11 @@ def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
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[SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
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>;
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// float, float, float, vcc
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def AMDGPUFmasOp : SDTypeProfile<1, 4,
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[SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
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>;
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Nodes
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//
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@ -153,7 +158,7 @@ def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
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// Special case divide FMA with scale and flags (src0 = Quotient,
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// src1 = Denominator, src2 = Numerator).
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def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
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def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
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// Single or double precision division fixup.
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// Special case divide fixup and flags(src0 = Quotient, src1 =
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@ -1300,6 +1300,28 @@ multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
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P.NumSrcArgs, P.HasModifiers
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>;
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// Special case for v_div_fmas_{f32|f64}, since it seems to be the
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// only VOP instruction that implicitly reads VCC.
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multiclass VOP3_VCC_Inst <vop3 op, string opName,
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VOPProfile P,
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SDPatternOperator node = null_frag> : VOP3_Helper <
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op, opName,
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P.Outs,
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(ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
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InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
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InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
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ClampMod:$clamp,
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omod:$omod),
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" $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
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(i1 VCC)))],
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3, 1
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>;
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multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
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string opName, list<dag> pattern> :
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VOP3b_3_m <
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@ -1744,14 +1744,27 @@ let SchedRW = [WriteDouble, WriteSALU] in {
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defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
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} // let SchedRW = [WriteDouble]
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let isCommutable = 1 in {
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defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
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let isCommutable = 1, Uses = [VCC] in {
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// v_div_fmas_f32:
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// result = src0 * src1 + src2
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// if (vcc)
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// result *= 2^32
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//
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defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
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VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
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>;
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let SchedRW = [WriteDouble] in {
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defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
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// v_div_fmas_f64:
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// result = src0 * src1 + src2
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// if (vcc)
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// result *= 2^64
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//
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defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
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VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
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>;
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} // End SchedRW = [WriteDouble]
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} // End isCommutable = 1
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@ -1,6 +1,10 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; FIXME: Enable for VI.
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare void @llvm.AMDGPU.barrier.global() nounwind noduplicate
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declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone
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declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
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@ -13,7 +17,8 @@ declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind re
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; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
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; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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@ -29,3 +34,104 @@ define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b,
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
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; SI: v_cmp_eq_i32_e64 vcc, s{{[0-9]+}}, 0
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
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%cmp = icmp eq i32 %i, 0
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%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
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; SI: s_mov_b64 vcc, 0
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
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; SI: s_mov_b64 vcc, -1
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-DAG: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
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; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0
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; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
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; SI: v_div_fmas_f32 {{v[0-9]+}}, [[B]], [[A]], [[C]]
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; SI: s_endpgm
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define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.a = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
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%gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
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%gep.out = getelementptr float addrspace(1)* %out, i32 2
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%a = load float addrspace(1)* %gep.a
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%b = load float addrspace(1)* %gep.b
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%c = load float addrspace(1)* %gep.c
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%cmp0 = icmp eq i32 %tid, 0
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%cmp1 = icmp ne i32 %d, 0
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%and = and i1 %cmp0, %cmp1
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%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
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store float %result, float addrspace(1)* %gep.out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
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; SI: v_cmp_eq_i32_e64 [[CMPTID:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
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; SI: s_and_saveexec_b64 [[CMPTID]], [[CMPTID]]
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; SI: s_xor_b64 [[CMPTID]], exec, [[CMPTID]]
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; SI: buffer_load_dword [[LOAD:v[0-9]+]]
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; SI: v_cmp_ne_i32_e64 [[CMPLOAD:s\[[0-9]+:[0-9]+\]]], [[LOAD]], 0
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; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, [[CMPLOAD]]
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; SI: BB6_2:
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; SI: s_or_b64 exec, exec, [[CMPTID]]
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; SI: v_cmp_ne_i32_e32 vcc, 0, v0
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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; SI: buffer_store_dword
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; SI: s_endpgm
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define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
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entry:
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.out = getelementptr float addrspace(1)* %out, i32 2
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%gep.a = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.b = getelementptr float addrspace(1)* %gep.a, i32 1
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%gep.c = getelementptr float addrspace(1)* %gep.a, i32 2
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%a = load float addrspace(1)* %gep.a
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%b = load float addrspace(1)* %gep.b
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%c = load float addrspace(1)* %gep.c
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%cmp0 = icmp eq i32 %tid, 0
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br i1 %cmp0, label %bb, label %exit
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bb:
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%val = load i32 addrspace(1)* %dummy
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%cmp1 = icmp ne i32 %val, 0
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br label %exit
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exit:
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%cond = phi i1 [false, %entry], [%cmp1, %bb]
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%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
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store float %result, float addrspace(1)* %gep.out, align 4
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ret void
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}
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