mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 22:04:55 +00:00
[x86] Silence unused diReg variable warning in non-asserting builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199812 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b92c3984b2
commit
929b0fb893
@ -1318,11 +1318,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
case X86II::Pseudo:
|
||||
llvm_unreachable("Pseudo instruction shouldn't be emitted");
|
||||
case X86II::RawFrmDstSrc: {
|
||||
unsigned diReg = MI.getOperand(0).getReg();
|
||||
unsigned siReg = MI.getOperand(1).getReg();
|
||||
assert(((siReg == X86::SI && diReg == X86::DI) ||
|
||||
(siReg == X86::ESI && diReg == X86::EDI) ||
|
||||
(siReg == X86::RSI && diReg == X86::RDI)) &&
|
||||
assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
|
||||
(siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
|
||||
(siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
|
||||
"SI and DI register sizes do not match");
|
||||
// Emit segment override opcode prefix as needed (not for %ds).
|
||||
if (MI.getOperand(2).getReg() != X86::DS)
|
||||
|
Loading…
Reference in New Issue
Block a user