From 929bdb23794b615dc6b0cc59db21f0450c3ce33b Mon Sep 17 00:00:00 2001 From: Weiming Zhao Date: Wed, 13 Nov 2013 18:29:49 +0000 Subject: [PATCH] Enable generating legacy IT block for AArch32 By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- lib/Target/ARM/ARMSubtarget.cpp | 29 +++++++++++++++++++++ lib/Target/ARM/ARMSubtarget.h | 6 +++++ lib/Target/ARM/ARMTargetMachine.cpp | 2 +- lib/Target/ARM/Thumb2ITBlockPass.cpp | 9 ++++--- test/CodeGen/ARM/2013-05-05-IfConvertBug.ll | 1 + test/CodeGen/Thumb2/thumb2-ifcvt1.ll | 5 ++-- test/CodeGen/Thumb2/thumb2-ifcvt2.ll | 2 ++ test/CodeGen/Thumb2/thumb2-ifcvt3.ll | 2 ++ test/CodeGen/Thumb2/v8_IT_1.ll | 1 + test/CodeGen/Thumb2/v8_IT_2.ll | 1 + test/CodeGen/Thumb2/v8_IT_3.ll | 2 ++ test/CodeGen/Thumb2/v8_IT_4.ll | 2 ++ test/CodeGen/Thumb2/v8_IT_5.ll | 1 + 14 files changed, 57 insertions(+), 8 deletions(-) diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7187d6a665b..b76ef9671bb 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -525,7 +525,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { MI->getParent()->getParent()->getInfo(); if (AFI->isThumb2Function()) { - if (getSubtarget().hasV8Ops()) + if (getSubtarget().restrictIT()) return isV8EligibleForIT(MI); } else { // non-Thumb if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index f59e522195c..a11629852ad 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -57,6 +57,23 @@ Align(cl::desc("Load/store alignment support"), "Allow unaligned memory accesses"), clEnumValEnd)); +enum ITMode { + DefaultIT, + RestrictedIT, + NoRestrictedIT +}; + +static cl::opt +IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), + cl::ZeroOrMore, + cl::values(clEnumValN(DefaultIT, "arm-default-it", + "Generate IT block based on arch"), + clEnumValN(RestrictedIT, "arm-restrict-it", + "Disallow deprecated IT based on ARMv8"), + clEnumValN(NoRestrictedIT, "arm-no-restrict-it", + "Allow IT blocks based on ARMv7"), + clEnumValEnd)); + ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, const TargetOptions &Options) : ARMGenSubtargetInfo(TT, CPU, FS) @@ -217,6 +234,18 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { break; } + switch (IT) { + case DefaultIT: + RestrictIT = hasV8Ops() ? true : false; + break; + case RestrictedIT: + RestrictIT = true; + break; + case NoRestrictedIT: + RestrictIT = false; + break; + } + // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. uint64_t Bits = getFeatureBits(); if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index aab93f1d6c0..5276901bbb9 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -177,6 +177,10 @@ protected: /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). bool AllowsUnalignedMem; + /// RestrictIT - If true, the subtarget disallows generation of deprecated IT + /// blocks to conform to ARMv8 rule. + bool RestrictIT; + /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith /// and such) instructions in Thumb2 code. bool Thumb2DSP; @@ -327,6 +331,8 @@ public: bool allowsUnalignedMem() const { return AllowsUnalignedMem; } + bool restrictIT() const { return RestrictIT; } + const std::string & getCPUString() const { return CPUString; } unsigned getMispredictionPenalty() const; diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index c78db54d8b0..c2bf7887787 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -198,7 +198,7 @@ bool ARMPassConfig::addPreSched2() { if (getOptLevel() != CodeGenOpt::None) { if (!getARMSubtarget().isThumb1Only()) { // in v8, IfConversion depends on Thumb instruction widths - if (getARMSubtarget().hasV8Ops() && + if (getARMSubtarget().restrictIT() && !getARMSubtarget().prefers32BitThumb()) addPass(createThumb2SizeReductionPass()); addPass(&IfConverterID); diff --git a/lib/Target/ARM/Thumb2ITBlockPass.cpp b/lib/Target/ARM/Thumb2ITBlockPass.cpp index 8f1ae2eaf8f..0b7d3bb7754 100644 --- a/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -28,7 +28,7 @@ namespace { static char ID; Thumb2ITBlockPass() : MachineFunctionPass(ID) {} - bool hasV8Ops; + bool restrictIT; const Thumb2InstrInfo *TII; const TargetRegisterInfo *TRI; ARMFunctionInfo *AFI; @@ -194,8 +194,9 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) { ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); unsigned Mask = 0, Pos = 3; - // v8 IT blocks are limited to one conditional op: skip the loop - if (!hasV8Ops) { + // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it + // is set: skip the loop + if (!restrictIT) { // Branches, including tricky ones like LDM_RET, need to end an IT // block so check the instruction we just put in the block. for (; MBBI != E && Pos && @@ -255,7 +256,7 @@ bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) { AFI = Fn.getInfo(); TII = static_cast(TM.getInstrInfo()); TRI = TM.getRegisterInfo(); - hasV8Ops = TM.getSubtarget().hasV8Ops(); + restrictIT = TM.getSubtarget().restrictIT(); if (!AFI->isThumbFunction()) return false; diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll index 2bebcf48185..c4f5f54c3af 100644 --- a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll +++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-V8 %s ; rdar://13782395 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll index 85943cfad7e..13a1ca2e26c 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s - +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it |FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: t1: ; CHECK: ittt ne @@ -74,7 +75,7 @@ entry: ; CHECK-LABEL: t3: ; CHECK: itt ge ; CHECK: movge r0, r1 -; CHECK: blge _foo +; CHECK: blge {{_?}}foo %tmp1 = icmp sgt i32 %a, 10 ; [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll index 788fa0674e6..403cd48035b 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-default-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-apple-ios -arm-no-restrict-it | FileCheck %s define void @foo(i32 %X, i32 %Y) { entry: diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index bcf10eff729..a71aa3fb613 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-apple-darwin -arm-no-restrict-it | FileCheck %s ; There shouldn't be a unconditional branch at end of bb52. ; rdar://7184787 diff --git a/test/CodeGen/Thumb2/v8_IT_1.ll b/test/CodeGen/Thumb2/v8_IT_1.ll index 9248378d059..30dbb4802b6 100644 --- a/test/CodeGen/Thumb2/v8_IT_1.ll +++ b/test/CodeGen/Thumb2/v8_IT_1.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv8 -mattr=+neon | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -mattr=+neon -arm-restrict-it | FileCheck %s ;CHECK-LABEL: select_s_v_v: ;CHECK-NOT: it diff --git a/test/CodeGen/Thumb2/v8_IT_2.ll b/test/CodeGen/Thumb2/v8_IT_2.ll index fe88316d147..170b4135b53 100644 --- a/test/CodeGen/Thumb2/v8_IT_2.ll +++ b/test/CodeGen/Thumb2/v8_IT_2.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } diff --git a/test/CodeGen/Thumb2/v8_IT_3.ll b/test/CodeGen/Thumb2/v8_IT_3.ll index 4d90891734d..4dca24629b0 100644 --- a/test/CodeGen/Thumb2/v8_IT_3.ll +++ b/test/CodeGen/Thumb2/v8_IT_3.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s ; RUN: llc < %s -mtriple=thumbv8 -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC %struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* } %struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 } diff --git a/test/CodeGen/Thumb2/v8_IT_4.ll b/test/CodeGen/Thumb2/v8_IT_4.ll index 45c79f430f1..5a80d8cd7b4 100644 --- a/test/CodeGen/Thumb2/v8_IT_4.ll +++ b/test/CodeGen/Thumb2/v8_IT_4.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -arm-restrict-it | FileCheck %s ; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -arm-restrict-it | FileCheck %s %"struct.__gnu_cxx::__normal_iterator, std::allocator > >" = type { i8* } %"struct.__gnu_cxx::new_allocator" = type <{ i8 }> diff --git a/test/CodeGen/Thumb2/v8_IT_5.ll b/test/CodeGen/Thumb2/v8_IT_5.ll index 3866068806e..30250c8d02f 100644 --- a/test/CodeGen/Thumb2/v8_IT_5.ll +++ b/test/CodeGen/Thumb2/v8_IT_5.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s ; CHECK: it ne ; CHECK-NEXT: cmpne ; CHECK-NEXT: beq