Add a LiveRangeEdit::Delegate protocol.

This will we used for keeping register allocator data structures up to date
while LiveRangeEdit is trimming live intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127300 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-03-09 00:57:29 +00:00
parent 2adc5b6a17
commit 92a55f4bdd
4 changed files with 38 additions and 7 deletions

View File

@ -333,7 +333,7 @@ void InlineSpiller::insertSpill(LiveInterval &NewLI,
void InlineSpiller::spill(LiveInterval *li, void InlineSpiller::spill(LiveInterval *li,
SmallVectorImpl<LiveInterval*> &newIntervals, SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> &spillIs) { const SmallVectorImpl<LiveInterval*> &spillIs) {
LiveRangeEdit edit(*li, newIntervals, &spillIs); LiveRangeEdit edit(*li, newIntervals, 0, &spillIs);
spill(edit); spill(edit);
if (VerifySpills) if (VerifySpills)
mf_.verify(&pass_, "After inline spill"); mf_.verify(&pass_, "After inline spill");

View File

@ -174,6 +174,8 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
ToShrink.insert(&LI); ToShrink.insert(&LI);
} }
if (delegate_)
delegate_->LRE_WillEraseInstruction(MI);
LIS.RemoveMachineInstrFromMaps(MI); LIS.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent(); MI->eraseFromParent();
} }

View File

@ -29,8 +29,17 @@ class MachineRegisterInfo;
class VirtRegMap; class VirtRegMap;
class LiveRangeEdit { class LiveRangeEdit {
public:
/// Callback methods for LiveRangeEdit owners.
struct Delegate {
/// Called immediately before erasing a dead machine instruction.
virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
};
private:
LiveInterval &parent_; LiveInterval &parent_;
SmallVectorImpl<LiveInterval*> &newRegs_; SmallVectorImpl<LiveInterval*> &newRegs_;
Delegate *const delegate_;
const SmallVectorImpl<LiveInterval*> *uselessRegs_; const SmallVectorImpl<LiveInterval*> *uselessRegs_;
/// firstNew_ - Index of the first register added to newRegs_. /// firstNew_ - Index of the first register added to newRegs_.
@ -66,9 +75,13 @@ public:
/// rematerializing values because they are about to be removed. /// rematerializing values because they are about to be removed.
LiveRangeEdit(LiveInterval &parent, LiveRangeEdit(LiveInterval &parent,
SmallVectorImpl<LiveInterval*> &newRegs, SmallVectorImpl<LiveInterval*> &newRegs,
Delegate *delegate,
const SmallVectorImpl<LiveInterval*> *uselessRegs = 0) const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
: parent_(parent), newRegs_(newRegs), uselessRegs_(uselessRegs), : parent_(parent), newRegs_(newRegs),
firstNew_(newRegs.size()), scannedRemattable_(false) {} delegate_(delegate),
uselessRegs_(uselessRegs),
firstNew_(newRegs.size()),
scannedRemattable_(false) {}
LiveInterval &getParent() const { return parent_; } LiveInterval &getParent() const { return parent_; }
unsigned getReg() const { return parent_.reg; } unsigned getReg() const { return parent_.reg; }

View File

@ -56,7 +56,10 @@ static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator); createGreedyRegisterAllocator);
namespace { namespace {
class RAGreedy : public MachineFunctionPass, public RegAllocBase { class RAGreedy : public MachineFunctionPass,
public RegAllocBase,
private LiveRangeEdit::Delegate {
// context // context
MachineFunction *MF; MachineFunction *MF;
BitVector ReservedRegs; BitVector ReservedRegs;
@ -157,6 +160,8 @@ public:
static char ID; static char ID;
private: private:
void LRE_WillEraseInstruction(MachineInstr*);
bool checkUncachedInterference(LiveInterval&, unsigned); bool checkUncachedInterference(LiveInterval&, unsigned);
LiveInterval *getSingleInterference(LiveInterval&, unsigned); LiveInterval *getSingleInterference(LiveInterval&, unsigned);
bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg); bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
@ -234,6 +239,17 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
//===----------------------------------------------------------------------===//
// LiveRangeEdit delegate methods
//===----------------------------------------------------------------------===//
void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
// LRE itself will remove from SlotIndexes and parent basic block.
VRM->RemoveMachineInstrFromMaps(MI);
}
void RAGreedy::releaseMemory() { void RAGreedy::releaseMemory() {
SpillerInstance.reset(0); SpillerInstance.reset(0);
LRStage.clear(); LRStage.clear();
@ -601,7 +617,7 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
SmallVector<IndexPair, 8> InterferenceRanges; SmallVector<IndexPair, 8> InterferenceRanges;
mapGlobalInterference(PhysReg, InterferenceRanges); mapGlobalInterference(PhysReg, InterferenceRanges);
LiveRangeEdit LREdit(VirtReg, NewVRegs); LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
SE->reset(LREdit); SE->reset(LREdit);
// Create the main cross-block interval. // Create the main cross-block interval.
@ -1129,7 +1145,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
<< '-' << Uses[BestAfter] << ", " << BestDiff << '-' << Uses[BestAfter] << ", " << BestDiff
<< ", " << (BestAfter - BestBefore + 1) << " instrs\n"); << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
LiveRangeEdit LREdit(VirtReg, NewVRegs); LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
SE->reset(LREdit); SE->reset(LREdit);
SE->openIntv(); SE->openIntv();
@ -1181,7 +1197,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
if (Stage < RS_Block) { if (Stage < RS_Block) {
SplitAnalysis::BlockPtrSet Blocks; SplitAnalysis::BlockPtrSet Blocks;
if (SA->getMultiUseBlocks(Blocks)) { if (SA->getMultiUseBlocks(Blocks)) {
LiveRangeEdit LREdit(VirtReg, NewVRegs); LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
SE->reset(LREdit); SE->reset(LREdit);
SE->splitSingleBlocks(Blocks); SE->splitSingleBlocks(Blocks);
setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block); setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);