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Remove isReg, isImm, and isMBB, and change all their users to use

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isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2007-09-14 20:33:02 +00:00
parent 693f541526
commit 92dfe2001e
17 changed files with 57 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
lib/CodeGen/MachineInstr.cpp
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@@ -188,7 +188,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
if (!isKill || MO.isKill())
return i;
}
@@ -200,7 +200,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return &MO;
}
return NULL;
@@ -225,7 +225,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
continue;
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
MachineOperand &MOp = getOperand(j);
@@ -248,7 +248,7 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
const MachineOperand &MO = MI->getOperand(i);
// Predicated operands must be last operands.
if (MO.isReg())
if (MO.isRegister())
addRegOperand(MO.getReg(), false);
else {
addImmOperand(MO.getImm());
@@ -319,7 +319,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
::print(getOperand(0), OS, TM);
if (getOperand(0).isDead())
OS << "<dead>";
@@ -337,7 +337,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
OS << " ";
::print(mop, OS, TM);
if (mop.isReg()) {
if (mop.isRegister()) {
if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
OS << "<";
bool NeedComma = false;
@@ -381,7 +381,7 @@ void MachineInstr::print(std::ostream &os) const {
for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
os << "\t" << getOperand(i);
if (getOperand(i).isReg() && getOperand(i).isDef())
if (getOperand(i).isRegister() && getOperand(i).isDef())
os << "<d>";
}