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Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -101,14 +101,30 @@ public:
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#endif
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struct LiveOutInfo {
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unsigned NumSignBits;
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unsigned NumSignBits : 31;
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bool IsValid : 1;
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APInt KnownOne, KnownZero;
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LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
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LiveOutInfo() : NumSignBits(0), IsValid(false), KnownOne(1, 0),
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KnownZero(1, 0) {}
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};
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/// LiveOutRegInfo - Information about live out vregs.
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IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
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/// VisitedBBs - Basic blocks that have been visited by reverse postorder.
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DenseSet<const BasicBlock*> VisitedBBs;
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/// AllPredsVisited - Tracks whether all predecessors of the current basic
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/// block have already been visited.
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bool AllPredsVisited;
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/// PHIDestRegs - Virtual registers that are the destinations of PHIs.
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DenseSet<unsigned> PHIDestRegs;
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/// PHISrcToDestMap - Maps the virtual register defining a PHI's source to the
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/// virtual register defining its destination.
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DenseMap<unsigned, unsigned> PHISrcToDestMap;
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/// PHINodesToUpdate - A list of phi instructions whose operand list will
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/// be updated after processing the current basic block.
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/// TODO: This isn't per-function state, it's per-basic-block state. But
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