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Merge information about the number of zero, one, and sign bits of live-out registers

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at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich
2011-02-22 00:46:27 +00:00
parent 63a8dae64d
commit 92efda7e91
5 changed files with 107 additions and 9 deletions
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8
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -644,7 +644,10 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
!RegisterVT.isInteger() || RegisterVT.isVector() ||
!FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
continue;
if (FuncInfo.PHIDestRegs.count(Regs[Part+i]) && !FuncInfo.AllPredsVisited)
continue;
const FunctionLoweringInfo::LiveOutInfo &LOI =
FuncInfo.LiveOutRegInfo[Regs[Part+i]];
@ -6466,6 +6469,9 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
}
}
if (!EnableFastISel)
FuncInfo.PHISrcToDestMap[Reg] = FuncInfo.ValueMap[PN];
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
SmallVector<EVT, 4> ValueVTs;