mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-30 02:25:19 +00:00
R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -17,6 +17,7 @@ using namespace llvm;
|
||||
|
||||
void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
StringRef Annot) {
|
||||
OS.flush();
|
||||
printInstruction(MI, OS);
|
||||
|
||||
printAnnotation(OS, Annot);
|
||||
@@ -67,11 +68,14 @@ void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O, StringRef Asm) {
|
||||
raw_ostream &O, StringRef Asm,
|
||||
StringRef Default) {
|
||||
const MCOperand &Op = MI->getOperand(OpNo);
|
||||
assert(Op.isImm());
|
||||
if (Op.getImm() == 1) {
|
||||
O << Asm;
|
||||
} else {
|
||||
O << Default;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -98,7 +102,7 @@ void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
|
||||
|
||||
void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printIfSet(MI, OpNo, O, " *");
|
||||
printIfSet(MI, OpNo, O.indent(20 - O.GetNumBytesInBuffer()), "*", " ");
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
|
||||
@@ -169,4 +173,29 @@ void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
|
||||
O << "." << chans[chan];
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
int BankSwizzle = MI->getOperand(OpNo).getImm();
|
||||
switch (BankSwizzle) {
|
||||
case 1:
|
||||
O << "BS:VEC_021";
|
||||
break;
|
||||
case 2:
|
||||
O << "BS:VEC_120";
|
||||
break;
|
||||
case 3:
|
||||
O << "BS:VEC_102";
|
||||
break;
|
||||
case 4:
|
||||
O << "BS:VEC_201";
|
||||
break;
|
||||
case 5:
|
||||
O << "BS:VEC_210";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#include "AMDGPUGenAsmWriter.inc"
|
||||
|
@@ -35,7 +35,8 @@ private:
|
||||
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm);
|
||||
void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
|
||||
StringRef Asm, StringRef Default = "");
|
||||
void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
@@ -47,6 +48,7 @@ private:
|
||||
void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
};
|
||||
|
||||
} // End namespace llvm
|
||||
|
@@ -78,7 +78,7 @@ def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
|
||||
let PrintMethod = "printSel";
|
||||
}
|
||||
def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
|
||||
let PrintMethod = "printSel";
|
||||
let PrintMethod = "printBankSwizzle";
|
||||
}
|
||||
|
||||
def LITERAL : InstFlag<"printLiteral">;
|
||||
@@ -358,9 +358,9 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
|
||||
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
|
||||
BANK_SWIZZLE:$bank_swizzle),
|
||||
!strconcat(" ", opName,
|
||||
"$clamp $dst$write$dst_rel$omod, "
|
||||
"$last$clamp $dst$write$dst_rel$omod, "
|
||||
"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
|
||||
"$literal $pred_sel$last"),
|
||||
"$pred_sel $bank_swizzle"),
|
||||
pattern,
|
||||
itin>,
|
||||
R600ALU_Word0,
|
||||
@@ -399,10 +399,10 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
|
||||
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
|
||||
BANK_SWIZZLE:$bank_swizzle),
|
||||
!strconcat(" ", opName,
|
||||
"$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
|
||||
"$last$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
|
||||
"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
|
||||
"$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
|
||||
"$literal $pred_sel$last"),
|
||||
"$pred_sel $bank_swizzle"),
|
||||
pattern,
|
||||
itin>,
|
||||
R600ALU_Word0,
|
||||
@@ -436,11 +436,12 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
|
||||
R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
|
||||
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
|
||||
BANK_SWIZZLE:$bank_swizzle),
|
||||
!strconcat(" ", opName, "$clamp $dst$dst_rel, "
|
||||
!strconcat(" ", opName, "$last$clamp $dst$dst_rel, "
|
||||
"$src0_neg$src0$src0_rel, "
|
||||
"$src1_neg$src1$src1_rel, "
|
||||
"$src2_neg$src2$src2_rel, "
|
||||
"$literal $pred_sel$last"),
|
||||
"$pred_sel"
|
||||
"$bank_swizzle"),
|
||||
pattern,
|
||||
itin>,
|
||||
R600ALU_Word0,
|
||||
|
@@ -89,9 +89,9 @@ def ONE_INT : R600Reg<"1", 250>;
|
||||
def HALF : R600Reg<"0.5", 252>;
|
||||
def NEG_HALF : R600Reg<"-0.5", 252>;
|
||||
def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
|
||||
def ALU_LITERAL_Y : R600RegWithChan<"literal.x", 253, "Y">;
|
||||
def ALU_LITERAL_Z : R600RegWithChan<"literal.x", 253, "Z">;
|
||||
def ALU_LITERAL_W : R600RegWithChan<"literal.x", 253, "W">;
|
||||
def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
|
||||
def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
|
||||
def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
|
||||
def PV_X : R600RegWithChan<"PV.x", 254, "X">;
|
||||
def PV_Y : R600RegWithChan<"PV.y", 254, "Y">;
|
||||
def PV_Z : R600RegWithChan<"PV.z", 254, "Z">;
|
||||
|
Reference in New Issue
Block a user