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Expand the x86 V_SET0* pseudos right after register allocation.
This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -392,7 +392,7 @@ public:
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/// into real instructions. The target can edit MI in place, or it can insert
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/// into real instructions. The target can edit MI in place, or it can insert
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/// new instructions and erase MI. The function should return true if
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/// new instructions and erase MI. The function should return true if
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/// anything was changed.
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/// anything was changed.
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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return false;
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return false;
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}
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}
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@ -2391,6 +2391,37 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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NewMIs.push_back(MIB);
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NewMIs.push_back(MIB);
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}
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}
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/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
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/// instruction with two undef reads of the register being defined. This is
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/// used for mapping:
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/// %xmm4 = V_SET0
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/// to:
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/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
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///
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static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
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assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
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unsigned Reg = MI->getOperand(0).getReg();
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MI->setDesc(Desc);
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// MachineInstr::addOperand() will insert explicit operands before any
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// implicit operands.
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MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
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.addReg(Reg, RegState::Undef);
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// But we don't trust that.
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assert(MI->getOperand(1).getReg() == Reg &&
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MI->getOperand(2).getReg() == Reg && "Misplaced operand");
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return true;
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}
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bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
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switch (MI->getOpcode()) {
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case X86::V_SET0:
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return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr));
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}
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return false;
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}
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MachineInstr*
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MachineInstr*
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X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
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X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx, uint64_t Offset,
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int FrameIx, uint64_t Offset,
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@ -2679,13 +2710,8 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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case X86::AVX_SET0PDY:
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case X86::AVX_SET0PDY:
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Alignment = 32;
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Alignment = 32;
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break;
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break;
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case X86::V_SET0PS:
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case X86::V_SET0:
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case X86::V_SET0PD:
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case X86::V_SET0PI:
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case X86::V_SETALLONES:
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case X86::V_SETALLONES:
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case X86::AVX_SET0PS:
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case X86::AVX_SET0PD:
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case X86::AVX_SET0PI:
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case X86::AVX_SETALLONES:
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case X86::AVX_SETALLONES:
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Alignment = 16;
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Alignment = 16;
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break;
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break;
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@ -2722,13 +2748,8 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
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SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
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switch (LoadMI->getOpcode()) {
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switch (LoadMI->getOpcode()) {
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case X86::V_SET0PS:
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case X86::V_SET0:
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case X86::V_SET0PD:
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case X86::V_SET0PI:
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case X86::V_SETALLONES:
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case X86::V_SETALLONES:
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case X86::AVX_SET0PS:
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case X86::AVX_SET0PD:
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case X86::AVX_SET0PI:
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case X86::AVX_SET0PSY:
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case X86::AVX_SET0PSY:
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case X86::AVX_SET0PDY:
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case X86::AVX_SET0PDY:
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case X86::AVX_SETALLONES:
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case X86::AVX_SETALLONES:
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@ -2736,7 +2757,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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case X86::FsFLD0SS:
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case X86::FsFLD0SS:
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case X86::VFsFLD0SD:
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case X86::VFsFLD0SD:
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case X86::VFsFLD0SS: {
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case X86::VFsFLD0SS: {
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// Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
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// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
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// Create a constant-pool entry and operands to load from it.
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// Create a constant-pool entry and operands to load from it.
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// Medium and large mode can't fold loads this way.
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// Medium and large mode can't fold loads this way.
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@ -3316,7 +3337,6 @@ static const unsigned ReplaceableInstrs[][3] = {
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{ X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
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{ X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
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{ X86::ORPSrm, X86::ORPDrm, X86::PORrm },
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{ X86::ORPSrm, X86::ORPDrm, X86::PORrm },
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{ X86::ORPSrr, X86::ORPDrr, X86::PORrr },
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{ X86::ORPSrr, X86::ORPDrr, X86::PORrr },
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{ X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
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{ X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
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{ X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
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{ X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
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{ X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
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// AVX 128-bit support
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// AVX 128-bit support
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@ -3332,7 +3352,6 @@ static const unsigned ReplaceableInstrs[][3] = {
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{ X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
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{ X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
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{ X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
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{ X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
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{ X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
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{ X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
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{ X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
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{ X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
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{ X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
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{ X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
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{ X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
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// AVX 256-bit support
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// AVX 256-bit support
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@ -247,6 +247,9 @@ public:
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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virtual
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virtual
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx, uint64_t Offset,
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int FrameIx, uint64_t Offset,
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@ -260,26 +260,26 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
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// AVX & SSE - Zero/One Vectors
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// AVX & SSE - Zero/One Vectors
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Alias instructions that map zero vector to pxor / xorp* for sse.
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// Alias instruction that maps zero vector to pxor / xorp* for sse.
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// This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
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// swizzled by ExecutionDepsFix to pxor.
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-zeros value if folding it would be beneficial.
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// load of an all-zeros value if folding it would be beneficial.
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// JIT implementation, it does not expand the instructions below like
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// X86MCInstLower does.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1 in {
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isPseudo = 1 in {
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def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
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[(set VR128:$dst, (v4f32 immAllZerosV))]>;
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def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v2f64 immAllZerosV))]>;
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let ExeDomain = SSEPackedInt in
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def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllZerosV))]>;
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}
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}
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// The same as done above but for AVX. The 128-bit versions are the
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def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
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// same, but re-encoded. The 256-bit does not support PI version, and
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def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
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// doesn't need it because on sandy bridge the register is set to zero
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def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
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def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
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def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
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def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
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// The same as done above but for AVX. The 256-bit ISA does not support PI,
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// and doesn't need it because on sandy bridge the register is set to zero
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// at the rename stage without using any execution unit, so SET0PSY
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// at the rename stage without using any execution unit, so SET0PSY
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// and SET0PDY can be used for vector int instructions without penalty
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// and SET0PDY can be used for vector int instructions without penalty
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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@ -287,32 +287,22 @@ def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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// X86MCInstLower does.
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// X86MCInstLower does.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, Predicates = [HasAVX] in {
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isCodeGenOnly = 1, Predicates = [HasAVX] in {
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def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
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def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
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def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
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[(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
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def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
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[(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
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let ExeDomain = SSEPackedInt in
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def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllZerosV))]>;
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}
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}
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def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
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def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
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def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
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// AVX has no support for 256-bit integer instructions, but since the 128-bit
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// AVX has no support for 256-bit integer instructions, but since the 128-bit
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// VPXOR instruction writes zero to its upper part, it's safe build zeros.
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// VPXOR instruction writes zero to its upper part, it's safe build zeros.
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def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
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def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
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def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
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def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
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(SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
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(SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
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def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
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def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
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def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
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def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
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(SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
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(SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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// load of an all-ones value if folding it would be beneficial.
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@ -427,12 +417,12 @@ let Predicates = [HasSSE1] in {
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// MOVSS to the lower bits.
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// MOVSS to the lower bits.
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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(MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
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(MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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(MOVSSrr (v4f32 (V_SET0PS)),
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(MOVSSrr (v4f32 (V_SET0)),
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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(MOVSSrr (v4i32 (V_SET0PI)),
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(MOVSSrr (v4i32 (V_SET0)),
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(EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
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(EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
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}
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}
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@ -483,7 +473,7 @@ let Predicates = [HasSSE2] in {
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// MOVSD to the lower bits.
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// MOVSD to the lower bits.
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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(MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
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(MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
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}
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}
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let AddedComplexity = 20 in {
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let AddedComplexity = 20 in {
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@ -558,15 +548,15 @@ let Predicates = [HasAVX] in {
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// MOVS{S,D} to the lower bits.
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// MOVS{S,D} to the lower bits.
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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(VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
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(VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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(VMOVSSrr (v4f32 (AVX_SET0PS)),
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(VMOVSSrr (v4f32 (V_SET0)),
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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(VMOVSSrr (v4i32 (AVX_SET0PI)),
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(VMOVSSrr (v4i32 (V_SET0)),
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(EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
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(EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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(VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
|
(VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
|
||||||
}
|
}
|
||||||
|
|
||||||
let AddedComplexity = 20 in {
|
let AddedComplexity = 20 in {
|
||||||
@ -604,12 +594,12 @@ let Predicates = [HasAVX] in {
|
|||||||
def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
|
def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
|
||||||
(v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
|
(v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
|
||||||
(SUBREG_TO_REG (i32 0),
|
(SUBREG_TO_REG (i32 0),
|
||||||
(v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
|
(v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
|
||||||
sub_xmm)>;
|
sub_xmm)>;
|
||||||
def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
|
def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
|
||||||
(v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
|
(v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
|
||||||
(SUBREG_TO_REG (i64 0),
|
(SUBREG_TO_REG (i64 0),
|
||||||
(v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
|
(v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
|
||||||
sub_xmm)>;
|
sub_xmm)>;
|
||||||
|
|
||||||
// Extract and store.
|
// Extract and store.
|
||||||
|
@ -372,15 +372,9 @@ ReSimplify:
|
|||||||
case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
|
case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
|
||||||
case X86::VFsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
|
case X86::VFsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
|
||||||
case X86::VFsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
|
case X86::VFsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
|
||||||
case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
|
|
||||||
case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
|
|
||||||
case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
|
|
||||||
case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
|
case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
|
||||||
case X86::AVX_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::VXORPSrr); break;
|
|
||||||
case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
|
case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
|
||||||
case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break;
|
|
||||||
case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
|
case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
|
||||||
case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
|
|
||||||
case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
|
case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
|
||||||
|
|
||||||
case X86::MOV16r0:
|
case X86::MOV16r0:
|
||||||
|
Loading…
Reference in New Issue
Block a user