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Code Issues Projects Releases Wiki Activity

Switch a number of loops in lib/CodeGen over to range-based for-loops, now that

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the MachineRegisterInfo iterators are compatible with it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204075 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2014-03-17 19:36:09 +00:00
parent 7ad87e4d3b
commit 92fca73d52
17 changed files with 88 additions and 143 deletions
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8
lib/CodeGen/LiveDebugVariables.cpp
View File

@ -568,12 +568,10 @@ UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo,
// Collect all the (vreg, valno) pairs that are copies of LI.
SmallVector<std::pair<LiveInterval*, const VNInfo*>, 8> CopyValues;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(LI->reg),
UE = MRI.use_nodbg_end(); UI != UE; ++UI) {
MachineInstr *MI = UI->getParent();
for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg)) {
MachineInstr *MI = MO.getParent();
// Copies of the full value.
if (UI->getSubReg() || !MI->isCopy())
if (MO.getSubReg() || !MI->isCopy())
continue;
unsigned DstReg = MI->getOperand(0).getReg();

18
lib/CodeGen/LiveRangeCalc.cpp
View File

@ -41,9 +41,8 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
// Visit all def operands. If the same instruction has multiple defs of Reg,
// LR.createDeadDef() will deduplicate.
for (MachineRegisterInfo::def_iterator
I = MRI->def_begin(Reg), E = MRI->def_end(); I != E; ++I) {
const MachineInstr *MI = I->getParent();
for (MachineOperand &MO : MRI->def_operands(Reg)) {
const MachineInstr *MI = MO.getParent();
// Find the corresponding slot index.
SlotIndex Idx;
if (MI->isPHI())
@ -52,7 +51,7 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
else
// Instructions are either normal 'r', or early clobber 'e'.
Idx = Indexes->getInstructionIndex(MI)
.getRegSlot(I->isEarlyClobber());
.getRegSlot(MO.isEarlyClobber());
// Create the def in LR. This may find an existing def.
LR.createDeadDef(Idx, *Alloc);
@ -64,9 +63,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
assert(MRI && Indexes && "call reset() first");
// Visit all operands that read Reg. This may include partial defs.
for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
E = MRI->reg_nodbg_end(); I != E; ++I) {
MachineOperand &MO = *I;
for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
// Clear all kill flags. They will be reinserted after register allocation
// by LiveIntervalAnalysis::addKillFlags().
if (MO.isUse())
@ -75,7 +72,8 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
continue;
// MI is reading Reg. We may have visited MI before if it happens to be
// reading Reg multiple times. That is OK, extend() is idempotent.
const MachineInstr *MI = I->getParent();
const MachineInstr *MI = MO.getParent();
unsigned OpNo = (&MO - &MI->getOperand(0));
// Find the SlotIndex being read.
SlotIndex Idx;
@ -83,7 +81,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
// PHI operands are paired: (Reg, PredMBB).
// Extend the live range to be live-out from PredMBB.
Idx = Indexes->getMBBEndIdx(MI->getOperand(I.getOperandNo()+1).getMBB());
Idx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
} else {
// This is a normal instruction.
Idx = Indexes->getInstructionIndex(MI).getRegSlot();
@ -92,7 +90,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
if (MO.isDef()) {
if (MO.isEarlyClobber())
Idx = Idx.getRegSlot(true);
} else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) {
} else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
// FIXME: This would be a lot easier if tied early-clobber uses also
// had an early-clobber flag.
if (MI->getOperand(DefIdx).isEarlyClobber())

6
lib/CodeGen/LiveRangeEdit.cpp
View File

@ -167,10 +167,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
MachineInstr *DefMI = 0, *UseMI = 0;
// Check that there is a single def and a single use.
for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
E = MRI.reg_nodbg_end(); I != E; ++I) {
MachineOperand &MO = *I;
MachineInstr *MI = I->getParent();
for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
MachineInstr *MI = MO.getParent();
if (MO.isDef()) {
if (DefMI && DefMI != MI)
return false;

26
lib/CodeGen/MachineCSE.cpp
View File

@ -364,15 +364,11 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
TargetRegisterInfo::isVirtualRegister(Reg)) {
MayIncreasePressure = false;
SmallPtrSet<MachineInstr*, 8> CSUses;
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
CSUses.insert(&*I);
for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
CSUses.insert(&MI);
}
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
if (!CSUses.count(&*I)) {
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
if (!CSUses.count(&MI)) {
MayIncreasePressure = true;
break;
}
@ -403,11 +399,9 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
}
if (!HasVRegUse) {
bool HasNonCopyUse = false;
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
// Ignore copies.
if (!I->isCopyLike()) {
if (!MI.isCopyLike()) {
HasNonCopyUse = true;
break;
}
@ -420,11 +414,9 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
// it unless the defined value is already used in the BB of the new use.
bool HasPHI = false;
SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
HasPHI |= I->isPHI();
CSBBs.insert(I->getParent());
for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
HasPHI |= MI.isPHI();
CSBBs.insert(MI.getParent());
}
if (!HasPHI)

30
lib/CodeGen/MachineLICM.cpp
View File

@ -978,26 +978,23 @@ bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
unsigned Reg = MO->getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
for (MachineRegisterInfo::use_instr_iterator
UI = MRI->use_instr_begin(Reg), UE = MRI->use_instr_end();
UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
// A PHI may cause a copy to be inserted.
if (UseMI->isPHI()) {
if (UseMI.isPHI()) {
// A PHI inside the loop causes a copy because the live range of Reg is
// extended across the PHI.
if (CurLoop->contains(UseMI))
if (CurLoop->contains(&UseMI))
return true;
// A PHI in an exit block can cause a copy to be inserted if the PHI
// has multiple predecessors in the loop with different values.
// For now, approximate by rejecting all exit blocks.
if (isExitBlock(UseMI->getParent()))
if (isExitBlock(UseMI.getParent()))
return true;
continue;
}
// Look past copies as well.
if (UseMI->isCopy() && CurLoop->contains(UseMI))
Work.push_back(UseMI);
if (UseMI.isCopy() && CurLoop->contains(&UseMI))
Work.push_back(&UseMI);
}
}
} while (!Work.empty());
@ -1012,23 +1009,20 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
return false;
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
MachineInstr *UseMI = &*I;
if (UseMI->isCopyLike())
for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
if (UseMI.isCopyLike())
continue;
if (!CurLoop->contains(UseMI->getParent()))
if (!CurLoop->contains(UseMI.getParent()))
continue;
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = UseMI->getOperand(i);
for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = UseMI.getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (MOReg != Reg)
continue;
if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i))
return true;
}

20
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -77,11 +77,11 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
return false;
// Accumulate constraints from all uses.
for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
++I) {
for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
// Apply the effect of the given operand to NewRC.
MachineInstr *MI = I->getParent();
NewRC = MI->getRegClassConstraintEffect(I.getOperandNo(), NewRC, TII,
MachineInstr *MI = MO.getParent();
unsigned OpNo = &MO - &MI->getOperand(0);
NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
getTargetRegisterInfo());
if (!NewRC || NewRC == OldRC)
return false;
@ -126,8 +126,8 @@ void MachineRegisterInfo::clearVirtRegs() {
void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
#ifndef NDEBUG
bool Valid = true;
for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
MachineOperand *MO = &*I;
for (MachineOperand &M : reg_operands(Reg)) {
MachineOperand *MO = &M;
MachineInstr *MI = MO->getParent();
if (!MI) {
errs() << PrintReg(Reg, getTargetRegisterInfo())
@ -329,8 +329,8 @@ bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
/// optimization passes which extend register lifetimes and need only
/// preserve conservative kill flag information.
void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
UI->setIsKill(false);
for (MachineOperand &MO : use_operands(Reg))
MO.setIsKill(false);
}
bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
@ -392,8 +392,8 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
#ifndef NDEBUG
void MachineRegisterInfo::dumpUses(unsigned Reg) const {
for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
I->getParent()->dump();
for (MachineInstr &I : use_instructions(Reg))
I.dump();
}
#endif

27
lib/CodeGen/MachineSink.cpp
View File

@ -171,13 +171,12 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
// Predecessors according to CFG: BB#0 BB#1
// %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
BreakPHIEdge = true;
for (MachineRegisterInfo::use_nodbg_iterator
I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
I != E; ++I) {
MachineInstr *UseInst = I->getParent();
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
MachineInstr *UseInst = MO.getParent();
unsigned OpNo = &MO - &UseInst->getOperand(0);
MachineBasicBlock *UseBlock = UseInst->getParent();
if (!(UseBlock == MBB && UseInst->isPHI() &&
UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) {
UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
BreakPHIEdge = false;
break;
}
@ -185,16 +184,15 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
if (BreakPHIEdge)
return true;
for (MachineRegisterInfo::use_nodbg_iterator
I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
I != E; ++I) {
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
// Determine the block of the use.
MachineInstr *UseInst = I->getParent();
MachineInstr *UseInst = MO.getParent();
unsigned OpNo = &MO - &UseInst->getOperand(0);
MachineBasicBlock *UseBlock = UseInst->getParent();
if (UseInst->isPHI()) {
// PHI nodes use the operand in the predecessor block, not the block with
// the PHI.
UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB();
UseBlock = UseInst->getOperand(OpNo+1).getMBB();
} else if (UseBlock == DefMBB) {
LocalUse = true;
return false;
@ -450,12 +448,9 @@ bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
// Check if only use in post dominated block is PHI instruction.
bool NonPHIUse = false;
for (MachineRegisterInfo::use_instr_nodbg_iterator
I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end();
I != E; ++I) {
MachineInstr *UseInst = &*I;
MachineBasicBlock *UseBlock = UseInst->getParent();
if (UseBlock == SuccToSinkTo && !UseInst->isPHI())
for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
MachineBasicBlock *UseBlock = UseInst.getParent();
if (UseBlock == SuccToSinkTo && !UseInst.isPHI())
NonPHIUse = true;
}
if (!NonPHIUse)

6
lib/CodeGen/OptimizePHIs.cpp
View File

@ -139,10 +139,8 @@ bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
if (PHIsInCycle.size() == 16)
return false;
for (MachineRegisterInfo::use_instr_iterator I = MRI->use_instr_begin(DstReg),
E = MRI->use_instr_end(); I != E; ++I) {
MachineInstr *UseMI = &*I;
if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle))
for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle))
return false;
}

6
lib/CodeGen/PHIElimination.cpp
View File

@ -198,10 +198,8 @@ bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
/// This includes registers with no defs.
static bool isImplicitlyDefined(unsigned VirtReg,
const MachineRegisterInfo *MRI) {
for (MachineRegisterInfo::def_instr_iterator
DI = MRI->def_instr_begin(VirtReg), DE = MRI->def_instr_end();
DI != DE; ++DI)
if (!DI->isImplicitDef())
for (MachineInstr &DI : MRI->def_instructions(VirtReg))
if (!DI.isImplicitDef())
return false;
return true;
}

8
lib/CodeGen/PHIEliminationUtils.cpp
View File

@ -34,11 +34,9 @@ llvm::findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB,
// Discover any defs/uses in this basic block.
SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
for (MachineRegisterInfo::reg_instr_iterator
RI = MRI.reg_instr_begin(SrcReg), RE = MRI.reg_instr_end();
RI != RE; ++RI) {
if (RI->getParent() == MBB)
DefUsesInMBB.insert(&*RI);
for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
if (RI.getParent() == MBB)
DefUsesInMBB.insert(&RI);
}
MachineBasicBlock::iterator InsertPoint;

19
lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -187,10 +187,8 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
// The source has other uses. See if we can replace the other uses with use of
// the result of the extension.
SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
for (MachineRegisterInfo::use_instr_nodbg_iterator
UI = MRI->use_instr_nodbg_begin(DstReg), UE = MRI->use_instr_nodbg_end();
UI != UE; ++UI)
ReachedBBs.insert(UI->getParent());
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
ReachedBBs.insert(UI.getParent());
// Uses that are in the same BB of uses of the result of the instruction.
SmallVector<MachineOperand*, 8> Uses;
@ -199,10 +197,7 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallVector<MachineOperand*, 8> ExtendedUses;
bool ExtendLife = true;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
UI != UE; ++UI) {
MachineOperand &UseMO = *UI;
for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
MachineInstr *UseMI = UseMO.getParent();
if (UseMI == MI)
continue;
@ -270,11 +265,9 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
// Look for PHI uses of the extended result, we don't want to extend the
// liveness of a PHI input. It breaks all kinds of assumptions down
// stream. A PHI use is expected to be the kill of its source values.
for (MachineRegisterInfo::use_instr_nodbg_iterator
UI = MRI->use_instr_nodbg_begin(DstReg),
UE = MRI->use_instr_nodbg_end(); UI != UE; ++UI)
if (UI->isPHI())
PHIBBs.insert(UI->getParent());
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
if (UI.isPHI())
PHIBBs.insert(UI.getParent());
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
for (unsigned i = 0, e = Uses.size(); i != e; ++i) {

5
lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -80,10 +80,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
// For virtual registers, mark all uses as <undef>, and convert users to
// implicit-def when possible.
for (MachineRegisterInfo::use_nodbg_iterator UI =
MRI->use_nodbg_begin(Reg),
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
MachineOperand &MO = *UI;
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
MO.setIsUndef();
MachineInstr *UserMI = MO.getParent();
if (!canTurnIntoImplicitDef(UserMI))

14
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -620,16 +620,15 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
// If some of the uses of IntA.reg is already coalesced away, return false.
// It's not possible to determine whether it's safe to perform the coalescing.
for (MachineRegisterInfo::use_nodbg_iterator UI =
MRI->use_nodbg_begin(IntA.reg),
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
MachineInstr *UseMI = UI->getParent();
for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
MachineInstr *UseMI = MO.getParent();
unsigned OpNo = &MO - &UseMI->getOperand(0);
SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
if (US == IntA.end() || US->valno != AValNo)
continue;
// If this use is tied to a def, we can't rewrite the register.
if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
if (UseMI->isRegTiedToDefOperand(OpNo))
return false;
}
@ -910,10 +909,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
DstInt->removeValNo(DeadVNI);
// Find new undef uses.
for (MachineRegisterInfo::reg_nodbg_iterator
I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
I != E; ++I) {
MachineOperand &MO = *I;
for (MachineOperand &MO : MRI->reg_nodbg_operands(DstInt->reg)) {
if (MO.isDef() || MO.isUndef())
continue;
MachineInstr *MI = MO.getParent();

8
lib/CodeGen/SplitKit.cpp
View File

@ -131,11 +131,9 @@ void SplitAnalysis::analyzeUses() {
// Get use slots form the use-def chain.
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (MachineRegisterInfo::use_nodbg_iterator
I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
++I)
if (!I->isUndef())
UseSlots.push_back(LIS.getInstructionIndex(I->getParent()).getRegSlot());
for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
if (!MO.isUndef())
UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
array_pod_sort(UseSlots.begin(), UseSlots.end());

8
lib/CodeGen/TailDuplication.cpp
View File

@ -338,12 +338,10 @@ bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) {
static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
const MachineRegisterInfo *MRI) {
for (MachineRegisterInfo::use_instr_iterator UI = MRI->use_instr_begin(Reg),
UE = MRI->use_instr_end(); UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
if (UseMI->isDebugValue())
for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
if (UseMI.isDebugValue())
continue;
if (UseMI->getParent() != BB)
if (UseMI.getParent() != BB)
return true;
}
return false;

16
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -315,9 +315,7 @@ bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
unsigned &LastDef) {
LastDef = 0;
unsigned LastUse = Dist;
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
E = MRI->reg_end(); I != E; ++I) {
MachineOperand &MO = *I;
for (MachineOperand &MO : MRI->reg_operands(Reg)) {
MachineInstr *MI = MO.getParent();
if (MI->getParent() != MBB || MI->isDebugValue())
continue;
@ -914,19 +912,17 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
/// instruction too close to the defs of its register dependencies.
bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
MachineInstr *MI) {
for (MachineRegisterInfo::def_instr_iterator DI = MRI->def_instr_begin(Reg),
DE = MRI->def_instr_end(); DI != DE; ++DI) {
MachineInstr *DefMI = &*DI;
if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
continue;
if (DefMI == MI)
if (&DefMI == MI)
return true; // MI is defining something KillMI uses
DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
if (DDI == DistanceMap.end())
return true; // Below MI
unsigned DefDist = DDI->second;
assert(Dist > DefDist && "Visited def already?");
if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
return true;
}
return false;

6
lib/CodeGen/VirtRegMap.cpp
View File

@ -418,10 +418,8 @@ void VirtRegRewriter::rewrite() {
// Check if this register has a use that will impact the rest of the
// code. Uses in debug and noreturn instructions do not impact the
// generated code.
for (MachineRegisterInfo::reg_instr_nodbg_iterator It =
MRI->reg_instr_nodbg_begin(Reg),
EndIt = MRI->reg_instr_nodbg_end(); It != EndIt; ++It) {
if (!NoReturnInsts.count(&(*It))) {
for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
if (!NoReturnInsts.count(&It)) {
MRI->setPhysRegUsed(Reg);
break;
}