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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
ARM: Use range-based for loops in frame lowering.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205602 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -316,10 +316,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock::iterator Pos = ++GPRCS1Push;
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BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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unsigned Reg = I->getReg();
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int FI = I->getFrameIdx();
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for (const auto &Entry : CSI) {
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unsigned Reg = Entry.getReg();
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int FI = Entry.getFrameIdx();
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switch (Reg) {
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case ARM::R8:
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case ARM::R9:
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@ -382,10 +381,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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unsigned Reg = I->getReg();
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int FI = I->getFrameIdx();
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for (const auto &Entry : CSI) {
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unsigned Reg = Entry.getReg();
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int FI = Entry.getFrameIdx();
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switch (Reg) {
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case ARM::R8:
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case ARM::R9:
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@ -419,10 +417,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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} while (DPRCSPush->getOpcode() == ARM::VSTMDDB_UPD);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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unsigned Reg = I->getReg();
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int FI = I->getFrameIdx();
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for (const auto &Entry : CSI) {
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unsigned Reg = Entry.getReg();
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int FI = Entry.getFrameIdx();
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if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
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(Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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@ -1205,12 +1202,9 @@ bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
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const ARMBaseInstrInfo &TII) {
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unsigned FnSize = 0;
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for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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const MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
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I != E; ++I)
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FnSize += TII.GetInstSizeInBytes(I);
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for (auto &MBB : MF) {
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for (auto &MI : MBB)
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FnSize += TII.GetInstSizeInBytes(&MI);
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}
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return FnSize;
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}
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@ -1223,21 +1217,21 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
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const TargetFrameLowering *TFI) {
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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unsigned Limit = (1 << 12) - 1;
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for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
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for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
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I != E; ++I) {
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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if (!I->getOperand(i).isFI()) continue;
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (!MI.getOperand(i).isFI())
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continue;
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// When using ADDri to get the address of a stack object, 255 is the
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// largest offset guaranteed to fit in the immediate offset.
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if (I->getOpcode() == ARM::ADDri) {
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if (MI.getOpcode() == ARM::ADDri) {
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Limit = std::min(Limit, (1U << 8) - 1);
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break;
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}
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// Otherwise check the addressing mode.
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switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
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switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
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case ARMII::AddrMode3:
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case ARMII::AddrModeT2_i8:
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Limit = std::min(Limit, (1U << 8) - 1);
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