diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
index 954a3d7ac55..1acaef1b947 100644
--- a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
+++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
@@ -92,8 +92,6 @@ enum attributeBits {
                                         "operands change width")               \
   ENUM_ENTRY(IC_ADSIZE,             3,  "requires an ADSIZE prefix, so "       \
                                         "operands change width")               \
-  ENUM_ENTRY(IC_OPSIZE_ADSIZE,      3,  "requires both OPSIZE and ADSIZE "     \
-                                        "prefixes")                            \
   ENUM_ENTRY(IC_XD,                 2,  "may say something about the opcode "  \
                                         "but not the operands")                \
   ENUM_ENTRY(IC_XS,                 2,  "may say something about the opcode "  \
diff --git a/test/MC/Disassembler/X86/moffs.txt b/test/MC/Disassembler/X86/moffs.txt
new file mode 100644
index 00000000000..67d64e8719a
--- /dev/null
+++ b/test/MC/Disassembler/X86/moffs.txt
@@ -0,0 +1,86 @@
+# RUN: llvm-mc --hdis %s -triple=i686-linux-gnu-code16 | FileCheck --check-prefix=16 %s
+# RUN: llvm-mc --hdis %s -triple=i686-linux-gnu | FileCheck --check-prefix=32 %s
+# RUN: llvm-mc --hdis %s -triple=x86_64-linux-gnu | FileCheck --check-prefix=64 %s
+
+# 16: movb 0x5a5a, %al
+# 32: movb 0x5a5a5a5a, %al
+# 64: movabsb 0x5a5a5a5a5a5a5a5a, %al
+0xa0 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movb 0x5a5a5a5a, %al
+# 32: movb 0x5a5a, %al
+# 64: movabsb 0x5a5a5a5a, %al
+0x67 0xa0 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movw 0x5a5a, %ax
+# 32: movl 0x5a5a5a5a, %eax
+# 64: movabsl 0x5a5a5a5a5a5a5a5a, %eax
+0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movw 0x5a5a5a5a, %ax
+# 32: movl 0x5a5a, %eax
+# 64: movabsl 0x5a5a5a5a, %eax
+0x67 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl 0x5a5a, %eax
+# 32: movw 0x5a5a5a5a, %ax
+# 64: movabsw 0x5a5a5a5a5a5a5a5a, %ax
+0x66 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl 0x5a5a5a5a, %eax
+# 32: movw 0x5a5a, %ax
+# 64: movabsw 0x5a5a5a5a, %ax
+0x66 0x67 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl 0x5a5a5a5a, %eax
+# 32: movw 0x5a5a, %ax
+# 64: movabsw 0x5a5a5a5a, %ax
+0x67 0x66 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl %es:0x5a5a5a5a, %eax
+# 32: movw %es:0x5a5a, %ax
+# 64: movabsw %es:0x5a5a5a5a, %ax
+0x67 0x26 0x66 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+
+
+# 16: movb %al, 0x5a5a
+# 32: movb %al, 0x5a5a5a5a
+# 64: movabsb %al, 0x5a5a5a5a5a5a5a5a
+0xa2 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movb %al, 0x5a5a5a5a
+# 32: movb %al, 0x5a5a
+# 64: movabsb %al, 0x5a5a5a5a
+0x67 0xa2 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movw %ax, 0x5a5a
+# 32: movl %eax, 0x5a5a5a5a
+# 64: movabsl %eax, 0x5a5a5a5a5a5a5a5a
+0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movw %ax, %gs:0x5a5a5a5a
+# 32: movl %eax, %gs:0x5a5a
+# 64: movabsl %eax, %gs:0x5a5a5a5a
+0x65 0x67 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl %eax, 0x5a5a
+# 32: movw %ax, 0x5a5a5a5a
+# 64: movabsw %ax, 0x5a5a5a5a5a5a5a5a
+0x66 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl %eax, 0x5a5a5a5a
+# 32: movw %ax, 0x5a5a
+# 64: movabsw %ax, 0x5a5a5a5a
+0x66 0x67 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl %eax, 0x5a5a5a5a
+# 32: movw %ax, 0x5a5a
+# 64: movabsw %ax, 0x5a5a5a5a
+0x67 0x66 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
+# 16: movl %eax, %es:0x5a5a5a5a
+# 32: movw %ax, %es:0x5a5a
+# 64: movabsw %ax, %es:0x5a5a5a5a
+0x67 0x26 0x66 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
+
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index 0ccfac7855e..f9c3e1ab2fa 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -94,11 +94,8 @@ static inline bool inheritsFrom(InstructionContext child,
            inheritsFrom(child, IC_64BIT_XD)     ||
            inheritsFrom(child, IC_64BIT_XS));
   case IC_OPSIZE:
-    return (inheritsFrom(child, IC_64BIT_OPSIZE) ||
-            inheritsFrom(child, IC_OPSIZE_ADSIZE));
+    return inheritsFrom(child, IC_64BIT_OPSIZE);
   case IC_ADSIZE:
-    return inheritsFrom(child, IC_OPSIZE_ADSIZE);
-  case IC_OPSIZE_ADSIZE:
   case IC_64BIT_ADSIZE:
     return false;
   case IC_XD:
@@ -803,6 +800,15 @@ void DisassemblerTables::setTableFields(ModRMDecision     &decision,
         if(newInfo.filtered)
           continue; // filtered instructions get lowest priority
 
+        // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
+        // presence of the AdSize prefix. However, the disassembler doesn't
+        // care about that difference in the instruction definition; it
+        // handles 16-bit vs. 32-bit addressing for itself based purely
+        // on the 0x67 prefix and the CPU mode. So there's no need to
+        // disambiguate between them; just let them conflict/coexist.
+        if (previousInfo.name + "_16" == newInfo.name)
+          continue;
+
         if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
                                            newInfo.name == "XCHG32ar" ||
                                            newInfo.name == "XCHG32ar64" ||
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 019610e1471..c09abefeef6 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -468,8 +468,6 @@ InstructionContext RecognizableInstr::insnContext() const {
     else if (HasOpSizePrefix &&
              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
       insnContext = IC_XS_OPSIZE;
-    else if (HasOpSizePrefix && HasAdSizePrefix)
-      insnContext = IC_OPSIZE_ADSIZE;
     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
              Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
       insnContext = IC_OPSIZE;