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Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.

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Added generic vector types: VR64 and VR128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-02-21 01:38:21 +00:00
parent aea20f50e5
commit 933be3318b
2 changed files with 27 additions and 9 deletions
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8
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -113,10 +113,14 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
} else if (RC == &X86::FR32RegClass || RC == &X86::V4F32RegClass) {
} else if (RC == &X86::FR32RegClass) {
Opc = X86::FsMOVAPSrr;
} else if (RC == &X86::FR64RegClass || RC == &X86::V2F64RegClass) {
} else if (RC == &X86::FR64RegClass) {
Opc = X86::FsMOVAPDrr;
} else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrr;
} else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrr;
} else {
assert(0 && "Unknown regclass");
abort();

28
lib/Target/X86/X86RegisterInfo.td
View File

@ -140,13 +140,22 @@ def RST : RegisterClass<"X86", [f64], 32,
}
// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
// and V2I32, the 2 x i32 class.
def V8I8 : RegisterClass<"X86", [v8i8], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
MM6, MM7]>;
def V4I16 : RegisterClass<"X86", [v4i16], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
MM6, MM7]>;
def V2I32 : RegisterClass<"X86", [v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
MM6, MM7]>;
// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 class,
// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class.
def V8I8 : RegisterClass<"X86", [v8i8], 64,
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
def V4I16 : RegisterClass<"X86", [v4i16], 64,
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
def V2I32 : RegisterClass<"X86", [v2i32], 64,
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
def V16I8 : RegisterClass<"X86", [v16i8], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
def V8I16 : RegisterClass<"X86", [v8i16], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
def V4I32 : RegisterClass<"X86", [v4i32], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
def V2I64 : RegisterClass<"X86", [v2i64], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
// the 2 x f64 class.
@ -155,3 +164,8 @@ def V4F32 : RegisterClass<"X86", [v4f32], 128,
def V2F64 : RegisterClass<"X86", [v2f64], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
// Generic vector registers: VR64 and VR128.
def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;