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Revert svn r80498 and replace it with a different solution. The only problem

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I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-15 23:12:05 +00:00
parent 4fac9470c4
commit 934f98b536
1 changed files with 4 additions and 12 deletions
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16
lib/Target/ARM/ARMISelLowering.cpp
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@ -2695,18 +2695,10 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
SDValue Vec = Op.getOperand(0);
SDValue Lane = Op.getOperand(1);
// FIXME: This is invalid for 8 and 16-bit elements - the information about
// sign / zero extension is lost!
Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
if (VT.bitsLT(MVT::i32))
Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
else if (VT.bitsGT(MVT::i32))
Op = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op);
return Op;
assert(VT == MVT::i32 &&
Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
"unexpected type for custom-lowering vector extract");
return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
}
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {