mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
[AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.
Refactored through AVX512_maskable git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220806 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
59cb03d329
commit
9371efbcdb
@ -4273,32 +4273,24 @@ def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
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(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
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(VRCP28PDZrb VR512:$src)>;
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multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins_s, OpndItins itins_d> {
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def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
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EVEX, EVEX_V512;
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let mayLoad = 1 in
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def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst,
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(OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
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itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
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EVEX, EVEX_V512;
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let mayLoad = 1 in
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def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR512:$dst, (OpNode
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(v8f64 (bitconvert (memopv16f32 addr:$src)))))],
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itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
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multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
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SDNode OpNode, X86VectorVTInfo _>{
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defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src), OpcodeStr, "$src", "$src",
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(_.FloatVT (OpNode _.RC:$src))>, EVEX;
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let mayLoad = 1 in {
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src), OpcodeStr, "$src", "$src",
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(OpNode (_.FloatVT
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(bitconvert (_.LdFrag addr:$src))))>, EVEX;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.ScalarMemOp:$src), OpcodeStr,
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"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
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(OpNode (_.FloatVT
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(X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
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EVEX, EVEX_B;
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}
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}
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multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
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@ -4362,12 +4354,36 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
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}
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}
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multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
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v16f32_info>,
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EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
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v8f64_info>,
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EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
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// Define only if AVX512VL feature is present.
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let Predicates = [HasVLX] in {
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defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
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OpNode, v4f32x_info>,
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EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
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defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
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OpNode, v8f32x_info>,
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EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
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defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
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OpNode, v2f64x_info>,
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EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
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defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
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OpNode, v4f64x_info>,
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EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
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}
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}
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defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
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defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
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int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
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SSE_SQRTSS, SSE_SQRTSD>,
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avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
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SSE_SQRTPS, SSE_SQRTPD>;
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SSE_SQRTSS, SSE_SQRTSD>;
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let Predicates = [HasAVX512] in {
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def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
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@ -3417,6 +3417,118 @@
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// CHECK: encoding: [0x62,0xe2,0x7d,0x58,0x4e,0x82,0xfc,0xfd,0xff,0xff]
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vrsqrt14ps -516(%rdx){1to16}, %zmm16
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// CHECK: vsqrtpd %zmm19, %zmm19
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// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x51,0xdb]
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vsqrtpd %zmm19, %zmm19
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// CHECK: vsqrtpd %zmm19, %zmm19 {%k5}
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// CHECK: encoding: [0x62,0xa1,0xfd,0x4d,0x51,0xdb]
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vsqrtpd %zmm19, %zmm19 {%k5}
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// CHECK: vsqrtpd %zmm19, %zmm19 {%k5} {z}
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// CHECK: encoding: [0x62,0xa1,0xfd,0xcd,0x51,0xdb]
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vsqrtpd %zmm19, %zmm19 {%k5} {z}
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// CHECK: vsqrtpd (%rcx), %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x51,0x19]
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vsqrtpd (%rcx), %zmm19
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// CHECK: vsqrtpd 291(%rax,%r14,8), %zmm19
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// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x51,0x9c,0xf0,0x23,0x01,0x00,0x00]
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vsqrtpd 291(%rax,%r14,8), %zmm19
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// CHECK: vsqrtpd (%rcx){1to8}, %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x51,0x19]
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vsqrtpd (%rcx){1to8}, %zmm19
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// CHECK: vsqrtpd 8128(%rdx), %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x51,0x5a,0x7f]
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vsqrtpd 8128(%rdx), %zmm19
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// CHECK: vsqrtpd 8192(%rdx), %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x51,0x9a,0x00,0x20,0x00,0x00]
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vsqrtpd 8192(%rdx), %zmm19
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// CHECK: vsqrtpd -8192(%rdx), %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x51,0x5a,0x80]
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vsqrtpd -8192(%rdx), %zmm19
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// CHECK: vsqrtpd -8256(%rdx), %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x51,0x9a,0xc0,0xdf,0xff,0xff]
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vsqrtpd -8256(%rdx), %zmm19
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// CHECK: vsqrtpd 1016(%rdx){1to8}, %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x51,0x5a,0x7f]
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vsqrtpd 1016(%rdx){1to8}, %zmm19
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// CHECK: vsqrtpd 1024(%rdx){1to8}, %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x51,0x9a,0x00,0x04,0x00,0x00]
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vsqrtpd 1024(%rdx){1to8}, %zmm19
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// CHECK: vsqrtpd -1024(%rdx){1to8}, %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x51,0x5a,0x80]
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vsqrtpd -1024(%rdx){1to8}, %zmm19
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// CHECK: vsqrtpd -1032(%rdx){1to8}, %zmm19
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// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x51,0x9a,0xf8,0xfb,0xff,0xff]
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vsqrtpd -1032(%rdx){1to8}, %zmm19
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// CHECK: vsqrtps %zmm29, %zmm28
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// CHECK: encoding: [0x62,0x01,0x7c,0x48,0x51,0xe5]
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vsqrtps %zmm29, %zmm28
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// CHECK: vsqrtps %zmm29, %zmm28 {%k3}
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// CHECK: encoding: [0x62,0x01,0x7c,0x4b,0x51,0xe5]
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vsqrtps %zmm29, %zmm28 {%k3}
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// CHECK: vsqrtps %zmm29, %zmm28 {%k3} {z}
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// CHECK: encoding: [0x62,0x01,0x7c,0xcb,0x51,0xe5]
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vsqrtps %zmm29, %zmm28 {%k3} {z}
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// CHECK: vsqrtps (%rcx), %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x51,0x21]
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vsqrtps (%rcx), %zmm28
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// CHECK: vsqrtps 291(%rax,%r14,8), %zmm28
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// CHECK: encoding: [0x62,0x21,0x7c,0x48,0x51,0xa4,0xf0,0x23,0x01,0x00,0x00]
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vsqrtps 291(%rax,%r14,8), %zmm28
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// CHECK: vsqrtps (%rcx){1to16}, %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x58,0x51,0x21]
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vsqrtps (%rcx){1to16}, %zmm28
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// CHECK: vsqrtps 8128(%rdx), %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x51,0x62,0x7f]
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vsqrtps 8128(%rdx), %zmm28
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// CHECK: vsqrtps 8192(%rdx), %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x51,0xa2,0x00,0x20,0x00,0x00]
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vsqrtps 8192(%rdx), %zmm28
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// CHECK: vsqrtps -8192(%rdx), %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x51,0x62,0x80]
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vsqrtps -8192(%rdx), %zmm28
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// CHECK: vsqrtps -8256(%rdx), %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x48,0x51,0xa2,0xc0,0xdf,0xff,0xff]
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vsqrtps -8256(%rdx), %zmm28
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// CHECK: vsqrtps 508(%rdx){1to16}, %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x58,0x51,0x62,0x7f]
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vsqrtps 508(%rdx){1to16}, %zmm28
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// CHECK: vsqrtps 512(%rdx){1to16}, %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x58,0x51,0xa2,0x00,0x02,0x00,0x00]
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vsqrtps 512(%rdx){1to16}, %zmm28
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// CHECK: vsqrtps -512(%rdx){1to16}, %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x58,0x51,0x62,0x80]
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vsqrtps -512(%rdx){1to16}, %zmm28
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// CHECK: vsqrtps -516(%rdx){1to16}, %zmm28
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// CHECK: encoding: [0x62,0x61,0x7c,0x58,0x51,0xa2,0xfc,0xfd,0xff,0xff]
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vsqrtps -516(%rdx){1to16}, %zmm28
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// CHECK: vsubpd %zmm9, %zmm12, %zmm9
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// CHECK: encoding: [0x62,0x51,0x9d,0x48,0x5c,0xc9]
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vsubpd %zmm9, %zmm12, %zmm9
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@ -4432,6 +4432,230 @@
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// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x4e,0x9a,0xfc,0xfd,0xff,0xff]
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vrsqrt14ps -516(%rdx){1to8}, %ymm27
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// CHECK: vsqrtpd %xmm26, %xmm29
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// CHECK: encoding: [0x62,0x01,0xfd,0x08,0x51,0xea]
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vsqrtpd %xmm26, %xmm29
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// CHECK: vsqrtpd %xmm26, %xmm29 {%k3}
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// CHECK: encoding: [0x62,0x01,0xfd,0x0b,0x51,0xea]
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vsqrtpd %xmm26, %xmm29 {%k3}
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// CHECK: vsqrtpd %xmm26, %xmm29 {%k3} {z}
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// CHECK: encoding: [0x62,0x01,0xfd,0x8b,0x51,0xea]
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vsqrtpd %xmm26, %xmm29 {%k3} {z}
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// CHECK: vsqrtpd (%rcx), %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x51,0x29]
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vsqrtpd (%rcx), %xmm29
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// CHECK: vsqrtpd 291(%rax,%r14,8), %xmm29
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// CHECK: encoding: [0x62,0x21,0xfd,0x08,0x51,0xac,0xf0,0x23,0x01,0x00,0x00]
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vsqrtpd 291(%rax,%r14,8), %xmm29
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// CHECK: vsqrtpd (%rcx){1to2}, %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x51,0x29]
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vsqrtpd (%rcx){1to2}, %xmm29
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// CHECK: vsqrtpd 2032(%rdx), %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x51,0x6a,0x7f]
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vsqrtpd 2032(%rdx), %xmm29
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// CHECK: vsqrtpd 2048(%rdx), %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x51,0xaa,0x00,0x08,0x00,0x00]
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vsqrtpd 2048(%rdx), %xmm29
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// CHECK: vsqrtpd -2048(%rdx), %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x51,0x6a,0x80]
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vsqrtpd -2048(%rdx), %xmm29
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// CHECK: vsqrtpd -2064(%rdx), %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x51,0xaa,0xf0,0xf7,0xff,0xff]
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vsqrtpd -2064(%rdx), %xmm29
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// CHECK: vsqrtpd 1016(%rdx){1to2}, %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x51,0x6a,0x7f]
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vsqrtpd 1016(%rdx){1to2}, %xmm29
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// CHECK: vsqrtpd 1024(%rdx){1to2}, %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x51,0xaa,0x00,0x04,0x00,0x00]
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vsqrtpd 1024(%rdx){1to2}, %xmm29
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// CHECK: vsqrtpd -1024(%rdx){1to2}, %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x51,0x6a,0x80]
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vsqrtpd -1024(%rdx){1to2}, %xmm29
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// CHECK: vsqrtpd -1032(%rdx){1to2}, %xmm29
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// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x51,0xaa,0xf8,0xfb,0xff,0xff]
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vsqrtpd -1032(%rdx){1to2}, %xmm29
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// CHECK: vsqrtpd %ymm20, %ymm18
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// CHECK: encoding: [0x62,0xa1,0xfd,0x28,0x51,0xd4]
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vsqrtpd %ymm20, %ymm18
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// CHECK: vsqrtpd %ymm20, %ymm18 {%k3}
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// CHECK: encoding: [0x62,0xa1,0xfd,0x2b,0x51,0xd4]
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vsqrtpd %ymm20, %ymm18 {%k3}
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// CHECK: vsqrtpd %ymm20, %ymm18 {%k3} {z}
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// CHECK: encoding: [0x62,0xa1,0xfd,0xab,0x51,0xd4]
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vsqrtpd %ymm20, %ymm18 {%k3} {z}
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// CHECK: vsqrtpd (%rcx), %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x51,0x11]
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vsqrtpd (%rcx), %ymm18
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// CHECK: vsqrtpd 291(%rax,%r14,8), %ymm18
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// CHECK: encoding: [0x62,0xa1,0xfd,0x28,0x51,0x94,0xf0,0x23,0x01,0x00,0x00]
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vsqrtpd 291(%rax,%r14,8), %ymm18
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// CHECK: vsqrtpd (%rcx){1to4}, %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x51,0x11]
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vsqrtpd (%rcx){1to4}, %ymm18
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// CHECK: vsqrtpd 4064(%rdx), %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x51,0x52,0x7f]
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vsqrtpd 4064(%rdx), %ymm18
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// CHECK: vsqrtpd 4096(%rdx), %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x51,0x92,0x00,0x10,0x00,0x00]
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vsqrtpd 4096(%rdx), %ymm18
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// CHECK: vsqrtpd -4096(%rdx), %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x51,0x52,0x80]
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vsqrtpd -4096(%rdx), %ymm18
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// CHECK: vsqrtpd -4128(%rdx), %ymm18
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// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x51,0x92,0xe0,0xef,0xff,0xff]
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vsqrtpd -4128(%rdx), %ymm18
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|
||||
// CHECK: vsqrtpd 1016(%rdx){1to4}, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x51,0x52,0x7f]
|
||||
vsqrtpd 1016(%rdx){1to4}, %ymm18
|
||||
|
||||
// CHECK: vsqrtpd 1024(%rdx){1to4}, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x51,0x92,0x00,0x04,0x00,0x00]
|
||||
vsqrtpd 1024(%rdx){1to4}, %ymm18
|
||||
|
||||
// CHECK: vsqrtpd -1024(%rdx){1to4}, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x51,0x52,0x80]
|
||||
vsqrtpd -1024(%rdx){1to4}, %ymm18
|
||||
|
||||
// CHECK: vsqrtpd -1032(%rdx){1to4}, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x51,0x92,0xf8,0xfb,0xff,0xff]
|
||||
vsqrtpd -1032(%rdx){1to4}, %ymm18
|
||||
|
||||
// CHECK: vsqrtps %xmm28, %xmm19
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0x08,0x51,0xdc]
|
||||
vsqrtps %xmm28, %xmm19
|
||||
|
||||
// CHECK: vsqrtps %xmm28, %xmm19 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0x0f,0x51,0xdc]
|
||||
vsqrtps %xmm28, %xmm19 {%k7}
|
||||
|
||||
// CHECK: vsqrtps %xmm28, %xmm19 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0x8f,0x51,0xdc]
|
||||
vsqrtps %xmm28, %xmm19 {%k7} {z}
|
||||
|
||||
// CHECK: vsqrtps (%rcx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x51,0x19]
|
||||
vsqrtps (%rcx), %xmm19
|
||||
|
||||
// CHECK: vsqrtps 291(%rax,%r14,8), %xmm19
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0x08,0x51,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vsqrtps 291(%rax,%r14,8), %xmm19
|
||||
|
||||
// CHECK: vsqrtps (%rcx){1to4}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x18,0x51,0x19]
|
||||
vsqrtps (%rcx){1to4}, %xmm19
|
||||
|
||||
// CHECK: vsqrtps 2032(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x51,0x5a,0x7f]
|
||||
vsqrtps 2032(%rdx), %xmm19
|
||||
|
||||
// CHECK: vsqrtps 2048(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x51,0x9a,0x00,0x08,0x00,0x00]
|
||||
vsqrtps 2048(%rdx), %xmm19
|
||||
|
||||
// CHECK: vsqrtps -2048(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x51,0x5a,0x80]
|
||||
vsqrtps -2048(%rdx), %xmm19
|
||||
|
||||
// CHECK: vsqrtps -2064(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x51,0x9a,0xf0,0xf7,0xff,0xff]
|
||||
vsqrtps -2064(%rdx), %xmm19
|
||||
|
||||
// CHECK: vsqrtps 508(%rdx){1to4}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x18,0x51,0x5a,0x7f]
|
||||
vsqrtps 508(%rdx){1to4}, %xmm19
|
||||
|
||||
// CHECK: vsqrtps 512(%rdx){1to4}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x18,0x51,0x9a,0x00,0x02,0x00,0x00]
|
||||
vsqrtps 512(%rdx){1to4}, %xmm19
|
||||
|
||||
// CHECK: vsqrtps -512(%rdx){1to4}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x18,0x51,0x5a,0x80]
|
||||
vsqrtps -512(%rdx){1to4}, %xmm19
|
||||
|
||||
// CHECK: vsqrtps -516(%rdx){1to4}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x18,0x51,0x9a,0xfc,0xfd,0xff,0xff]
|
||||
vsqrtps -516(%rdx){1to4}, %xmm19
|
||||
|
||||
// CHECK: vsqrtps %ymm25, %ymm19
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0x28,0x51,0xd9]
|
||||
vsqrtps %ymm25, %ymm19
|
||||
|
||||
// CHECK: vsqrtps %ymm25, %ymm19 {%k2}
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0x2a,0x51,0xd9]
|
||||
vsqrtps %ymm25, %ymm19 {%k2}
|
||||
|
||||
// CHECK: vsqrtps %ymm25, %ymm19 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7c,0xaa,0x51,0xd9]
|
||||
vsqrtps %ymm25, %ymm19 {%k2} {z}
|
||||
|
||||
// CHECK: vsqrtps (%rcx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x28,0x51,0x19]
|
||||
vsqrtps (%rcx), %ymm19
|
||||
|
||||
// CHECK: vsqrtps 291(%rax,%r14,8), %ymm19
|
||||
// CHECK: encoding: [0x62,0xa1,0x7c,0x28,0x51,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vsqrtps 291(%rax,%r14,8), %ymm19
|
||||
|
||||
// CHECK: vsqrtps (%rcx){1to8}, %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x38,0x51,0x19]
|
||||
vsqrtps (%rcx){1to8}, %ymm19
|
||||
|
||||
// CHECK: vsqrtps 4064(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x28,0x51,0x5a,0x7f]
|
||||
vsqrtps 4064(%rdx), %ymm19
|
||||
|
||||
// CHECK: vsqrtps 4096(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x28,0x51,0x9a,0x00,0x10,0x00,0x00]
|
||||
vsqrtps 4096(%rdx), %ymm19
|
||||
|
||||
// CHECK: vsqrtps -4096(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x28,0x51,0x5a,0x80]
|
||||
vsqrtps -4096(%rdx), %ymm19
|
||||
|
||||
// CHECK: vsqrtps -4128(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x28,0x51,0x9a,0xe0,0xef,0xff,0xff]
|
||||
vsqrtps -4128(%rdx), %ymm19
|
||||
|
||||
// CHECK: vsqrtps 508(%rdx){1to8}, %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x38,0x51,0x5a,0x7f]
|
||||
vsqrtps 508(%rdx){1to8}, %ymm19
|
||||
|
||||
// CHECK: vsqrtps 512(%rdx){1to8}, %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x38,0x51,0x9a,0x00,0x02,0x00,0x00]
|
||||
vsqrtps 512(%rdx){1to8}, %ymm19
|
||||
|
||||
// CHECK: vsqrtps -512(%rdx){1to8}, %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x38,0x51,0x5a,0x80]
|
||||
vsqrtps -512(%rdx){1to8}, %ymm19
|
||||
|
||||
// CHECK: vsqrtps -516(%rdx){1to8}, %ymm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x7c,0x38,0x51,0x9a,0xfc,0xfd,0xff,0xff]
|
||||
vsqrtps -516(%rdx){1to8}, %ymm19
|
||||
|
||||
// CHECK: vmovapd %xmm22, (%rcx)
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x29,0x31]
|
||||
vmovapd %xmm22, (%rcx)
|
||||
|
||||
@ -171,12 +171,17 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_OPSIZE:
|
||||
return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
|
||||
inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
|
||||
case IC_EVEX_B:
|
||||
return false;
|
||||
case IC_EVEX_W:
|
||||
case IC_EVEX_W_XS:
|
||||
case IC_EVEX_W_XD:
|
||||
case IC_EVEX_W_OPSIZE:
|
||||
return false;
|
||||
case IC_EVEX_L:
|
||||
case IC_EVEX_L_K_B:
|
||||
case IC_EVEX_L_KZ_B:
|
||||
case IC_EVEX_L_B:
|
||||
case IC_EVEX_L_XS:
|
||||
case IC_EVEX_L_XD:
|
||||
case IC_EVEX_L_OPSIZE:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user