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https://github.com/c64scene-ar/llvm-6502.git
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Now that the ISel is available, it's possible to create a default instruction
scheduler creator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29452 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,6 +38,7 @@ namespace {
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(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
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(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
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(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
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(void) llvm::createDefaultScheduler(NULL, NULL, NULL);
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}
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} ForceCodegenLinking; // Force link by creating a global definition.
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@ -258,6 +258,11 @@ namespace llvm {
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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}
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#endif
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@ -42,6 +42,8 @@ public:
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SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
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TargetLowering &getTargetLowering() { return TLI; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnFunction(Function &Fn);
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@ -68,7 +68,8 @@ namespace {
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cl::desc("Instruction schedulers available:"));
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static RegisterScheduler
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defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
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defaultListDAGScheduler("default", " Best scheduler for the target",
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createDefaultScheduler);
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} // namespace
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namespace {
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@ -123,6 +124,24 @@ namespace {
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}
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namespace llvm {
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//===--------------------------------------------------------------------===//
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB) {
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TargetLowering &TLI = IS->getTargetLowering();
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
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return createTDListDAGScheduler(IS, DAG, BB);
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} else {
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assert(TLI.getSchedulingPreference() ==
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TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
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return createBURRListDAGScheduler(IS, DAG, BB);
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}
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}
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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@ -3614,21 +3633,7 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
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RegisterScheduler::getDefault();
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if (!Ctor) {
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if (std::string("default") == std::string(ISHeuristic)) {
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
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Ctor = RegisterScheduler::FindCtor("list-td");
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else {
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assert(TLI.getSchedulingPreference() ==
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TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
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Ctor = RegisterScheduler::FindCtor("list-burr");
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}
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assert(Ctor && "Default instruction scheduler not present");
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if (!Ctor) Ctor = RegisterScheduler::FindCtor("none");
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} else {
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Ctor = RegisterScheduler::FindCtor(ISHeuristic);
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}
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RegisterScheduler::setDefault(Ctor);
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}
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