From 93803535ad7b487e85b537e81adffb471b7d09a9 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Wed, 1 Oct 2014 21:07:07 +0000 Subject: [PATCH] [x86] Merge the remaining test cases into vector-blend.ll and remove all the ISA-specific test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218818 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/avx2-blend.ll | 11 --- test/CodeGen/X86/sse2-blend.ll | 57 ------------ test/CodeGen/X86/sse41-blend.ll | 150 ------------------------------- test/CodeGen/X86/vector-blend.ll | 117 ++++++++++++++++++++++++ 4 files changed, 117 insertions(+), 218 deletions(-) delete mode 100644 test/CodeGen/X86/avx2-blend.ll delete mode 100644 test/CodeGen/X86/sse2-blend.ll delete mode 100644 test/CodeGen/X86/sse41-blend.ll diff --git a/test/CodeGen/X86/avx2-blend.ll b/test/CodeGen/X86/avx2-blend.ll deleted file mode 100644 index b02442b6fad..00000000000 --- a/test/CodeGen/X86/avx2-blend.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s - -define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) { -; CHECK-LABEL: constant_pblendvb_avx2: -; CHECK: vmovdqa -; CHECK: vpblendvb - %1 = select <32 x i1> , <32 x i8> %xyzw, <32 x i8> %abcd - ret <32 x i8> %1 -} - -declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/test/CodeGen/X86/sse2-blend.ll b/test/CodeGen/X86/sse2-blend.ll deleted file mode 100644 index c63ff72b480..00000000000 --- a/test/CodeGen/X86/sse2-blend.ll +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse4.1 | FileCheck %s - -; CHECK-LABEL: vsel_float -; CHECK-NOT: xorps -; CHECK: movss -; CHECK-NOT: orps -; CHECK: ret -define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) { - %A = load <4 x float>* %v1 - %B = load <4 x float>* %v2 - %vsel = select <4 x i1> , <4 x float> %A, <4 x float> %B - store <4 x float > %vsel, <4 x float>* %v1 - ret void -} - -; CHECK-LABEL: vsel_i32 -; CHECK-NOT: xorps -; CHECK: movss -; CHECK-NOT: orps -; CHECK: ret -define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) { - %A = load <4 x i32>* %v1 - %B = load <4 x i32>* %v2 - %vsel = select <4 x i1> , <4 x i32> %A, <4 x i32> %B - store <4 x i32 > %vsel, <4 x i32>* %v1 - ret void -} - -; Without forcing instructions, fall back to the preferred PS domain. -; CHECK-LABEL: vsel_i64 -; CHECK: andnps -; CHECK: orps -; CHECK: ret - -define void@vsel_i64(<2 x i64>* %v1, <2 x i64>* %v2) { - %A = load <2 x i64>* %v1 - %B = load <2 x i64>* %v2 - %vsel = select <2 x i1> , <2 x i64> %A, <2 x i64> %B - store <2 x i64 > %vsel, <2 x i64>* %v1 - ret void -} - -; Without forcing instructions, fall back to the preferred PS domain. -; CHECK-LABEL: vsel_double -; CHECK: andnps -; CHECK: orps -; CHECK: ret - -define void@vsel_double(<2 x double>* %v1, <2 x double>* %v2) { - %A = load <2 x double>* %v1 - %B = load <2 x double>* %v2 - %vsel = select <2 x i1> , <2 x double> %A, <2 x double> %B - store <2 x double > %vsel, <2 x double>* %v1 - ret void -} - - diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll deleted file mode 100644 index 3992da0b512..00000000000 --- a/test/CodeGen/X86/sse41-blend.ll +++ /dev/null @@ -1,150 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s - -;CHECK-LABEL: vsel_float: -;CHECK: blendps -;CHECK: ret -define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { - %vsel = select <4 x i1> , <4 x float> %v1, <4 x float> %v2 - ret <4 x float> %vsel -} - - -;CHECK-LABEL: vsel_4xi8: -;CHECK: blendps -;CHECK: ret -define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { - %vsel = select <4 x i1> , <4 x i8> %v1, <4 x i8> %v2 - ret <4 x i8> %vsel -} - -;CHECK-LABEL: vsel_4xi16: -;CHECK: blendps -;CHECK: ret -define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { - %vsel = select <4 x i1> , <4 x i16> %v1, <4 x i16> %v2 - ret <4 x i16> %vsel -} - - -;CHECK-LABEL: vsel_i32: -;CHECK: blendps -;CHECK: ret -define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { - %vsel = select <4 x i1> , <4 x i32> %v1, <4 x i32> %v2 - ret <4 x i32> %vsel -} - - -;CHECK-LABEL: vsel_double: -;CHECK: movsd -;CHECK: ret -define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) { - %vsel = select <4 x i1> , <4 x double> %v1, <4 x double> %v2 - ret <4 x double> %vsel -} - - -;CHECK-LABEL: vsel_i64: -;CHECK: movsd -;CHECK: ret -define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) { - %vsel = select <4 x i1> , <4 x i64> %v1, <4 x i64> %v2 - ret <4 x i64> %vsel -} - - -;CHECK-LABEL: vsel_i8: -;CHECK: pblendvb -;CHECK: ret -define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { - %vsel = select <16 x i1> , <16 x i8> %v1, <16 x i8> %v2 - ret <16 x i8> %vsel -} - -;; TEST blend + compares -; CHECK: A -define <2 x double> @A(<2 x double> %x, <2 x double> %y) { - ; CHECK: cmplepd - ; CHECK: blendvpd - %max_is_x = fcmp oge <2 x double> %x, %y - %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y - ret <2 x double> %max -} - -; CHECK: B -define <2 x double> @B(<2 x double> %x, <2 x double> %y) { - ; CHECK: cmpnlepd - ; CHECK: blendvpd - %min_is_x = fcmp ult <2 x double> %x, %y - %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y - ret <2 x double> %min -} - -; CHECK: float_crash -define void @float_crash() nounwind { -entry: - %merge205vector_func.i = select <4 x i1> undef, <4 x double> undef, <4 x double> undef - %extract214vector_func.i = extractelement <4 x double> %merge205vector_func.i, i32 0 - store double %extract214vector_func.i, double addrspace(1)* undef, align 8 - ret void -} - -; If we can figure out a blend has a constant mask, we should emit the -; blend instruction with an immediate mask -define <2 x double> @constant_blendvpd(<2 x double> %xy, <2 x double> %ab) { -; In this case, we emit a simple movss -; CHECK-LABEL: constant_blendvpd -; CHECK: movsd -; CHECK: ret - %1 = select <2 x i1> , <2 x double> %xy, <2 x double> %ab - ret <2 x double> %1 -} - -define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) { -; CHECK-LABEL: constant_blendvps -; CHECK-NOT: mov -; CHECK: blendps $7 -; CHECK: ret - %1 = select <4 x i1> , <4 x float> %xyzw, <4 x float> %abcd - ret <4 x float> %1 -} - -define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) { -; CHECK-LABEL: constant_pblendvb: -; CHECK: movaps -; CHECK: pblendvb -; CHECK: ret - %1 = select <16 x i1> , <16 x i8> %xyzw, <16 x i8> %abcd - ret <16 x i8> %1 -} - -declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) -declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) -declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) - -;; 2 tests for shufflevectors that optimize to blend + immediate -; CHECK-LABEL: @blend_shufflevector_4xfloat -; CHECK: blendps $6, %xmm1, %xmm0 -; CHECK: ret -define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) { - %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> - ret <4 x float> %1 -} - -; CHECK-LABEL: @blend_shufflevector_8xi16 -; CHECK: pblendw $134, %xmm1, %xmm0 -; CHECK: ret -define <8 x i16> @blend_shufflevector_8xi16(<8 x i16> %a, <8 x i16> %b) { - %1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> - ret <8 x i16> %1 -} - -; PR20648 - a blend of constants isn't really a blend; it's just a constant pool load. -; CHECK-LABEL: @does_not_blend -; CHECK: movaps -; CHECK-NEXT: ret -define <4 x i32> @does_not_blend() { - %select = select <4 x i1> , <4 x i32> , <4 x i32> - ret <4 x i32> %select -} - diff --git a/test/CodeGen/X86/vector-blend.ll b/test/CodeGen/X86/vector-blend.ll index 1465d8c61bd..7e5c10dd762 100644 --- a/test/CodeGen/X86/vector-blend.ll +++ b/test/CodeGen/X86/vector-blend.ll @@ -49,6 +49,72 @@ define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) { ret <4 x float> %vsel } +define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { +; SSE2-LABEL: vsel_4xi8: +; SSE2: ## BB#0: +; SSE2-NEXT: andps {{.*}}, %xmm1 +; SSE2-NEXT: andps {{.*}}, %xmm0 +; SSE2-NEXT: orps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSSE3-LABEL: vsel_4xi8: +; SSSE3: ## BB#0: +; SSSE3-NEXT: andps {{.*}}, %xmm1 +; SSSE3-NEXT: andps {{.*}}, %xmm0 +; SSSE3-NEXT: orps %xmm1, %xmm0 +; SSSE3-NEXT: retq +; +; SSE41-LABEL: vsel_4xi8: +; SSE41: ## BB#0: +; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] +; SSE41-NEXT: retq +; +; AVX1-LABEL: vsel_4xi8: +; AVX1: ## BB#0: +; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] +; AVX1-NEXT: retq +; +; AVX2-LABEL: vsel_4xi8: +; AVX2: ## BB#0: +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] +; AVX2-NEXT: retq + %vsel = select <4 x i1> , <4 x i8> %v1, <4 x i8> %v2 + ret <4 x i8> %vsel +} + +define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { +; SSE2-LABEL: vsel_4xi16: +; SSE2: ## BB#0: +; SSE2-NEXT: andps {{.*}}, %xmm1 +; SSE2-NEXT: andps {{.*}}, %xmm0 +; SSE2-NEXT: orps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSSE3-LABEL: vsel_4xi16: +; SSSE3: ## BB#0: +; SSSE3-NEXT: andps {{.*}}, %xmm1 +; SSSE3-NEXT: andps {{.*}}, %xmm0 +; SSSE3-NEXT: orps %xmm1, %xmm0 +; SSSE3-NEXT: retq +; +; SSE41-LABEL: vsel_4xi16: +; SSE41: ## BB#0: +; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; SSE41-NEXT: retq +; +; AVX1-LABEL: vsel_4xi16: +; AVX1: ## BB#0: +; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; AVX1-NEXT: retq +; +; AVX2-LABEL: vsel_4xi16: +; AVX2: ## BB#0: +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; AVX2-NEXT: retq + %vsel = select <4 x i1> , <4 x i16> %v1, <4 x i16> %v2 + ret <4 x i16> %vsel +} + define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { ; SSE2-LABEL: vsel_i32: ; SSE2: ## BB#0: @@ -440,6 +506,57 @@ define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) ret <8 x float> %1 } +define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) { +; SSE2-LABEL: constant_pblendvb_avx2: +; SSE2: ## BB#0: +; SSE2-NEXT: movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255] +; SSE2-NEXT: andps %xmm4, %xmm2 +; SSE2-NEXT: movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0] +; SSE2-NEXT: andps %xmm5, %xmm0 +; SSE2-NEXT: orps %xmm2, %xmm0 +; SSE2-NEXT: andps %xmm4, %xmm3 +; SSE2-NEXT: andps %xmm5, %xmm1 +; SSE2-NEXT: orps %xmm3, %xmm1 +; SSE2-NEXT: retq +; +; SSSE3-LABEL: constant_pblendvb_avx2: +; SSSE3: ## BB#0: +; SSSE3-NEXT: movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255] +; SSSE3-NEXT: andps %xmm4, %xmm2 +; SSSE3-NEXT: movaps {{.*#+}} xmm5 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0] +; SSSE3-NEXT: andps %xmm5, %xmm0 +; SSSE3-NEXT: orps %xmm2, %xmm0 +; SSSE3-NEXT: andps %xmm4, %xmm3 +; SSSE3-NEXT: andps %xmm5, %xmm1 +; SSSE3-NEXT: orps %xmm3, %xmm1 +; SSSE3-NEXT: retq +; +; SSE41-LABEL: constant_pblendvb_avx2: +; SSE41: ## BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm4 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0] +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: pblendvb %xmm1, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: movdqa %xmm3, %xmm1 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_pblendvb_avx2: +; AVX1: ## BB#0: +; AVX1-NEXT: vandps {{.*}}, %ymm1, %ymm1 +; AVX1-NEXT: vandps {{.*}}, %ymm0, %ymm0 +; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_pblendvb_avx2: +; AVX2: ## BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0] +; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: retq + %1 = select <32 x i1> , <32 x i8> %xyzw, <32 x i8> %abcd + ret <32 x i8> %1 +} + declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)