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Make data structures private.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-01-11 23:19:08 +00:00
parent 337a269dec
commit 9384111e90
3 changed files with 17 additions and 11 deletions
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18
lib/CodeGen/RegAllocBase.h
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@ -62,7 +62,6 @@ class RegAllocBase {
// registers may have changed. // registers may have changed.
unsigned UserTag; unsigned UserTag;
protected:
// Array of LiveIntervalUnions indexed by physical register. // Array of LiveIntervalUnions indexed by physical register.
class LiveUnionArray { class LiveUnionArray {
unsigned NumRegs; unsigned NumRegs;
@ -83,17 +82,19 @@ protected:
} }
}; };
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
VirtRegMap *VRM;
LiveIntervals *LIS;
RegisterClassInfo RegClassInfo;
LiveUnionArray PhysReg2LiveUnion; LiveUnionArray PhysReg2LiveUnion;
// Current queries, one per physreg. They must be reinitialized each time we // Current queries, one per physreg. They must be reinitialized each time we
// query on a new live virtual register. // query on a new live virtual register.
OwningArrayPtr<LiveIntervalUnion::Query> Queries; OwningArrayPtr<LiveIntervalUnion::Query> Queries;
protected:
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
VirtRegMap *VRM;
LiveIntervals *LIS;
RegisterClassInfo RegClassInfo;
RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {} RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
virtual ~RegAllocBase() {} virtual ~RegAllocBase() {}
@ -110,6 +111,11 @@ protected:
return Queries[PhysReg]; return Queries[PhysReg];
} }
// Get direct access to the underlying LiveIntervalUnion for PhysReg.
LiveIntervalUnion &getLiveUnion(unsigned PhysReg) {
return PhysReg2LiveUnion[PhysReg];
}
// Invalidate all cached information about virtual registers - live ranges may // Invalidate all cached information about virtual registers - live ranges may
// have changed. // have changed.
void invalidateVirtRegs() { ++UserTag; } void invalidateVirtRegs() { ++UserTag; }

6
lib/CodeGen/RegAllocBasic.cpp
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@ -250,9 +250,9 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
// Found an available register. // Found an available register.
return PhysReg; return PhysReg;
} }
Queries[interfReg].collectInterferingVRegs(1); LiveIntervalUnion::Query &IntfQ = query(VirtReg, interfReg);
LiveInterval *interferingVirtReg = IntfQ.collectInterferingVRegs(1);
Queries[interfReg].interferingVRegs().front(); LiveInterval *interferingVirtReg = IntfQ.interferingVRegs().front();
// The current VirtReg must either be spillable, or one of its interferences // The current VirtReg must either be spillable, or one of its interferences
// must have less spill weight. // must have less spill weight.

4
lib/CodeGen/RegAllocGreedy.cpp
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@ -1288,7 +1288,7 @@ void RAGreedy::calcGapWeights(unsigned PhysReg,
// surrounding the instruction. The exception is interference before // surrounding the instruction. The exception is interference before
// StartIdx and after StopIdx. // StartIdx and after StopIdx.
// //
LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx); LiveIntervalUnion::SegmentIter IntI = getLiveUnion(*AI).find(StartIdx);
for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) { for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
// Skip the gaps before IntI. // Skip the gaps before IntI.
while (Uses[Gap+1].getBoundaryIndex() < IntI.start()) while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
@ -1624,7 +1624,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
ExtraRegInfo.clear(); ExtraRegInfo.clear();
ExtraRegInfo.resize(MRI->getNumVirtRegs()); ExtraRegInfo.resize(MRI->getNumVirtRegs());
NextCascade = 1; NextCascade = 1;
IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI); IntfCache.init(MF, &getLiveUnion(0), Indexes, TRI);
GlobalCand.resize(32); // This will grow as needed. GlobalCand.resize(32); // This will grow as needed.
allocatePhysRegs(); allocatePhysRegs();