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add support for loading FP constants +0.0 and +1.0 to the dag isel,

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stop pretending -0.0 and -1.0 are machine constants


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-11-02 02:35:04 +00:00
parent 7c22575e32
commit 93856802ae
2 changed files with 8 additions and 3 deletions
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8
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -321,6 +321,14 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
/* todo:
* case ISD::DYNAMIC_STACKALLOC:
*/
case ISD::ConstantFP: {
if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
return CurDAG->getRegister(IA64::F0, MVT::f64); // load 0.0
else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
return CurDAG->getRegister(IA64::F1, MVT::f64); // load 1.0
else
assert(0 && "Unexpected FP constant!");
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex();

3
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -80,9 +80,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
addLegalFPImmediate(+0.0);
addLegalFPImmediate(+1.0);
addLegalFPImmediate(-0.0);
addLegalFPImmediate(-1.0);
}
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.