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Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.
Now there is no special treatment of instructions that redefine part of a super-register. Instead, the super-register is marked with <imp-use,kill> and <imp-def>. For instance, from LowerSubregs on ARM: subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5 subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def> subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6 subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78466 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -112,9 +112,6 @@ public:
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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/// isSuperRegUsed - Test if a super register is currently being used.
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bool isSuperRegUsed(unsigned Reg) const;
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/// getRegsUsed - return all registers currently in use in used.
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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void getRegsUsed(BitVector &used, bool includeReserved);
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@ -270,14 +270,15 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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MachineBasicBlock::iterator CopyMI = MI;
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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--CopyMI;
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// INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
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if (!MI->getOperand(1).isUndef())
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
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// Transfer the kill/dead flags, if needed.
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// Transfer the kill/dead flags, if needed.
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if (MI->getOperand(0).isDead()) {
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if (MI->getOperand(0).isDead()) {
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TransferDeadFlag(MI, DstSubReg, TRI);
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TransferDeadFlag(MI, DstSubReg, TRI);
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// Also add a SrcReg<imp-kill> of the super register.
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} else {
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
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// Make sure the full DstReg is live after this replacement.
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} else if (MI->getOperand(1).isUndef()) {
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// If SrcReg was marked <undef> we must make sure it is alive after this
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// replacement. Add a SrcReg<imp-def> operand.
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
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}
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}
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@ -30,35 +30,6 @@
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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using namespace llvm;
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/// RedefinesSuperRegPart - Return true if the specified register is redefining
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/// part of a super-register.
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static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
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const TargetRegisterInfo *TRI) {
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bool SeenSuperUse = false;
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bool SeenSuperDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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if (TRI->isSuperRegister(SubReg, MO.getReg())) {
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if (MO.isUse())
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SeenSuperUse = true;
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else if (MO.isImplicit())
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SeenSuperDef = true;
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}
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}
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return SeenSuperDef && SeenSuperUse;
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}
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bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
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for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs)
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if (isUsed(SuperReg))
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return true;
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return false;
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}
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/// setUsed - Set the register and its sub-registers as being used.
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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RegsAvailable.reset(Reg);
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@ -74,8 +45,7 @@ void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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unsigned SubReg = *SubRegs; ++SubRegs)
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if (!RedefinesSuperRegPart(MI, Reg, TRI))
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RegsAvailable.set(SubReg);
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RegsAvailable.set(SubReg);
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}
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}
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void RegScavenger::initRegState() {
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void RegScavenger::initRegState() {
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@ -257,7 +227,7 @@ void RegScavenger::forward() {
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"Using an early clobbered register!");
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"Using an early clobbered register!");
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} else {
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} else {
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assert(MO.isDef());
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assert(MO.isDef());
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assert((KillRegs.test(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
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assert((KillRegs.test(Reg) || isUnused(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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"Re-defining a live register!");
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}
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}
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