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Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.

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Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78466 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-08-08 13:19:10 +00:00
parent dffb051c21
commit 9390cd0e86
3 changed files with 9 additions and 41 deletions
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3
include/llvm/CodeGen/RegisterScavenging.h
View File

@ -112,9 +112,6 @@ public:
bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
/// isSuperRegUsed - Test if a super register is currently being used.
bool isSuperRegUsed(unsigned Reg) const;
/// getRegsUsed - return all registers currently in use in used.
void getRegsUsed(BitVector &used, bool includeReserved);

11
lib/CodeGen/LowerSubregs.cpp
View File

@ -270,14 +270,15 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
// INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
if (!MI->getOperand(1).isUndef())
CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead()) {
TransferDeadFlag(MI, DstSubReg, TRI);
// Also add a SrcReg<imp-kill> of the super register.
CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
} else if (MI->getOperand(1).isUndef()) {
// If SrcReg was marked <undef> we must make sure it is alive after this
// replacement. Add a SrcReg<imp-def> operand.
} else {
// Make sure the full DstReg is live after this replacement.
CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
}

32
lib/CodeGen/RegisterScavenging.cpp
View File

@ -30,35 +30,6 @@
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
/// RedefinesSuperRegPart - Return true if the specified register is redefining
/// part of a super-register.
static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
const TargetRegisterInfo *TRI) {
bool SeenSuperUse = false;
bool SeenSuperDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isUndef())
continue;
if (TRI->isSuperRegister(SubReg, MO.getReg())) {
if (MO.isUse())
SeenSuperUse = true;
else if (MO.isImplicit())
SeenSuperDef = true;
}
}
return SeenSuperDef && SeenSuperUse;
}
bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
unsigned SuperReg = *SuperRegs; ++SuperRegs)
if (isUsed(SuperReg))
return true;
return false;
}
/// setUsed - Set the register and its sub-registers as being used.
void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg);
@ -74,7 +45,6 @@ void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
if (!RedefinesSuperRegPart(MI, Reg, TRI))
RegsAvailable.set(SubReg);
}
@ -257,7 +227,7 @@ void RegScavenger::forward() {
"Using an early clobbered register!");
} else {
assert(MO.isDef());
assert((KillRegs.test(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
assert((KillRegs.test(Reg) || isUnused(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
}