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Rest of addrmode2 instruction encodings.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-09-01 01:27:33 +00:00
parent 17222df0ec
commit 93912739c9
2 changed files with 106 additions and 14 deletions
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100
lib/Target/ARM/ARMInstrFormats.td
View File

@ -142,6 +142,8 @@ class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
asm, "", pattern> {
let Inst{26-27} = 1;
}
// loads
class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
@ -159,6 +161,24 @@ class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit
}
// stores
class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
@ -173,20 +193,92 @@ class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
asm, "", pattern>;
// Pre-indexed ops
class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
// loads
class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern>;
asm, cstr, pattern> {
let Inst{20} = 1; // load bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 1; // load bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
// stores
class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
}
class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern>;
// Post-indexed ops
class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
// loads
class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern>;
asm, cstr,pattern> {
let Inst{20} = 1; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
}
class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 1; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
}
// stores
class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
}
class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
let Inst{20} = 0; // load bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
}
class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,

20
lib/Target/ARM/ARMInstrInfo.td
View File

@ -621,11 +621,11 @@ def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
[]>, Requires<[IsARM, HasV5T]>;
// Indexed loads
def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb),
def LDR_PRE : AI2ldwpr<0x0, (outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb),
def LDR_POST : AI2ldwpo<0x0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), LdFrm,
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
@ -637,11 +637,11 @@ def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb),
def LDRB_PRE : AI2ldbpr<0x1, (outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm,
"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb),
def LDRB_POST : AI2ldbpo<0x1, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am2offset:$offset), LdFrm,
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
@ -663,7 +663,7 @@ def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
}
// Store
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
def STR : AI2stw<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>;
@ -672,7 +672,7 @@ def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
"str", "h $src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
def STRB : AI2stb<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", "b $src, $addr",
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
@ -683,13 +683,13 @@ def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
[]>, Requires<[IsARM, HasV5T]>;
// Indexed stores
def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb),
def STR_PRE : AI2stwpr<0x0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
"str", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STR_POST : AI2po<0x0, (outs GPR:$base_wb),
def STR_POST : AI2stwpo<0x0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb,
@ -707,13 +707,13 @@ def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>;
def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb),
def STRB_PRE : AI2stbpr<0x1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", "b $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,