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MIR Parser: make the machine instruction parsing interface more consistent. NFC.
This commit refactors the interface for machine instruction parser. It adopts the pattern of returning a bool and passing in the result in the first argument that is used by the other parsing methods for the the method 'parse' and the function 'parseMachineInstr'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241085 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -63,7 +63,7 @@ public:
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/// This function always return true.
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bool error(StringRef::iterator Loc, const Twine &Msg);
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MachineInstr *parse();
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bool parse(MachineInstr *&MI);
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bool parseRegister(unsigned &Reg);
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bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
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@ -129,7 +129,7 @@ bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
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return true;
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}
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MachineInstr *MIParser::parse() {
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bool MIParser::parse(MachineInstr *&MI) {
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lex();
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// Parse any register operands before '='
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@ -138,32 +138,28 @@ MachineInstr *MIParser::parse() {
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SmallVector<MachineOperand, 8> Operands;
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if (Token.isRegister()) {
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if (parseRegisterOperand(MO, /*IsDef=*/true))
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return nullptr;
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return true;
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Operands.push_back(MO);
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if (Token.isNot(MIToken::equal)) {
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error("expected '='");
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return nullptr;
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}
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if (Token.isNot(MIToken::equal))
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return error("expected '='");
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lex();
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}
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unsigned OpCode;
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if (Token.isError() || parseInstruction(OpCode))
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return nullptr;
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return true;
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// TODO: Parse the instruction flags and memory operands.
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// Parse the remaining machine operands.
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while (Token.isNot(MIToken::Eof)) {
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if (parseMachineOperand(MO))
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return nullptr;
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return true;
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Operands.push_back(MO);
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if (Token.is(MIToken::Eof))
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break;
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if (Token.isNot(MIToken::comma)) {
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error("expected ',' before the next machine operand");
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return nullptr;
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}
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if (Token.isNot(MIToken::comma))
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return error("expected ',' before the next machine operand");
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lex();
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}
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@ -184,10 +180,10 @@ MachineInstr *MIParser::parse() {
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// TODO: Determine the implicit behaviour when implicit register flags are
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// parsed.
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auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
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MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
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for (const auto &Operand : Operands)
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MI->addOperand(MF, Operand);
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return MI;
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return false;
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}
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bool MIParser::parseInstruction(unsigned &OpCode) {
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@ -390,9 +386,9 @@ const uint32_t *MIParser::getRegMask(StringRef Identifier) {
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return RegMaskInfo->getValue();
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}
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MachineInstr *
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llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src,
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const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
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const SlotMapping &IRSlots, SMDiagnostic &Error) {
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return MIParser(SM, MF, Error, Src, MBBSlots, IRSlots).parse();
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bool llvm::parseMachineInstr(
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MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF, StringRef Src,
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const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
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const SlotMapping &IRSlots, SMDiagnostic &Error) {
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return MIParser(SM, MF, Error, Src, MBBSlots, IRSlots).parse(MI);
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}
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@ -26,10 +26,10 @@ struct SlotMapping;
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class SMDiagnostic;
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class SourceMgr;
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MachineInstr *
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parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src,
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const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
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const SlotMapping &IRSlots, SMDiagnostic &Error);
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bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF,
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StringRef Src,
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const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
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const SlotMapping &IRSlots, SMDiagnostic &Error);
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} // end namespace llvm
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@ -265,13 +265,13 @@ bool MIRParserImpl::initializeMachineBasicBlock(
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// Parse the instructions.
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for (const auto &MISource : YamlMBB.Instructions) {
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SMDiagnostic Error;
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if (auto *MI = parseMachineInstr(SM, MF, MISource.Value, MBBSlots, IRSlots,
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Error)) {
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MBB.insert(MBB.end(), MI);
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continue;
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MachineInstr *MI = nullptr;
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if (parseMachineInstr(MI, SM, MF, MISource.Value, MBBSlots, IRSlots,
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Error)) {
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reportDiagnostic(diagFromMIStringDiag(Error, MISource.SourceRange));
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return true;
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}
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reportDiagnostic(diagFromMIStringDiag(Error, MISource.SourceRange));
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return true;
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MBB.insert(MBB.end(), MI);
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}
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return false;
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}
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