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When checking for sret-demotion, it needs to use legal types. When using the return value of an sret-demoted call, it needs to use possibly illegal types that match the declared Type of the callee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93667 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -800,18 +800,19 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
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SDNodeOrder, Chain, NULL);
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}
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/// Get the EVTs and ArgFlags collections that represent the return type
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/// of the given function. This does not require a DAG or a return value, and
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/// is suitable for use before any DAGs for the function are constructed.
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/// Get the EVTs and ArgFlags collections that represent the legalized return
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/// type of the given function. This does not require a DAG or a return value,
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/// and is suitable for use before any DAGs for the function are constructed.
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static void getReturnInfo(const Type* ReturnType,
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Attributes attr, SmallVectorImpl<EVT> &OutVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
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TargetLowering &TLI,
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SmallVectorImpl<uint64_t> *Offsets = 0) {
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, ReturnType, ValueVTs, Offsets);
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ComputeValueVTs(TLI, ReturnType, ValueVTs);
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unsigned NumValues = ValueVTs.size();
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if ( NumValues == 0 ) return;
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if (NumValues == 0) return;
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unsigned Offset = 0;
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for (unsigned j = 0, f = NumValues; j != f; ++j) {
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EVT VT = ValueVTs[j];
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@ -834,6 +835,9 @@ static void getReturnInfo(const Type* ReturnType,
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unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
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EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
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unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
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PartVT.getTypeForEVT(ReturnType->getContext()));
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// 'inreg' on function refers to return value
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ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
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if (attr & Attribute::InReg)
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@ -848,6 +852,11 @@ static void getReturnInfo(const Type* ReturnType,
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for (unsigned i = 0; i < NumParts; ++i) {
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OutVTs.push_back(PartVT);
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OutFlags.push_back(Flags);
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if (Offsets)
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{
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Offsets->push_back(Offset);
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Offset += PartSize;
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}
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}
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}
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}
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@ -5098,16 +5107,37 @@ void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
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SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
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MVT::Other, &Chains[0], NumValues);
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PendingLoads.push_back(Chain);
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// Collect the legal value parts into potentially illegal values
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// that correspond to the original function's return values.
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SmallVector<EVT, 4> RetTys;
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RetTy = FTy->getReturnType();
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ComputeValueVTs(TLI, RetTy, RetTys);
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ISD::NodeType AssertOp = ISD::DELETED_NODE;
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SmallVector<SDValue, 4> ReturnValues;
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unsigned CurReg = 0;
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for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
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EVT VT = RetTys[I];
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EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
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unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
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SDValue ReturnValue =
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getCopyFromParts(DAG, getCurDebugLoc(), SDNodeOrder, &Values[CurReg], NumRegs,
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RegisterVT, VT, AssertOp);
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ReturnValues.push_back(ReturnValue);
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if (DisableScheduling)
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DAG.AssignOrdering(ReturnValue.getNode(), SDNodeOrder);
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CurReg += NumRegs;
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}
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SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
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DAG.getVTList(&RetTys[0], RetTys.size()),
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&ReturnValues[0], ReturnValues.size());
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SDValue MV = DAG.getNode(ISD::MERGE_VALUES,
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getCurDebugLoc(),
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DAG.getVTList(&OutVTs[0], NumValues),
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&Values[0], NumValues);
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setValue(CS.getInstruction(), MV);
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setValue(CS.getInstruction(), Res);
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if (DisableScheduling) {
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DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
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DAG.AssignOrdering(MV.getNode(), SDNodeOrder);
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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}
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12
test/CodeGen/X86/bigstructret2.ll
Normal file
12
test/CodeGen/X86/bigstructret2.ll
Normal file
@ -0,0 +1,12 @@
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; RUN: llc < %s -march=x86 -o %t
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%0 = type { i64, i64 }
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declare fastcc %0 @ReturnBigStruct() nounwind readnone
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define void @test(%0* %p) {
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%1 = call fastcc %0 @ReturnBigStruct()
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store %0 %1, %0* %p
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ret void
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}
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