From 93b3b928d70df956b81ab1bffb7e8bab4b0c8fd7 Mon Sep 17 00:00:00 2001
From: Mon P Wang <wangmp@apple.com>
Date: Mon, 15 Dec 2008 21:44:00 +0000
Subject: [PATCH] Added support for splitting and scalarizing vector shifts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61050 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/LegalizeTypes.h       |  1 +
 .../SelectionDAG/LegalizeVectorTypes.cpp       | 18 ++++++++++++++++++
 test/CodeGen/X86/vshift_scalar.ll              | 11 +++++++++++
 test/CodeGen/X86/vshift_split2.ll              | 11 +++++++++++
 4 files changed, 41 insertions(+)
 create mode 100644 test/CodeGen/X86/vshift_scalar.ll
 create mode 100644 test/CodeGen/X86/vshift_split2.ll

diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 36c89adebc6..9a42c5656ee 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -496,6 +496,7 @@ private:
   // Vector Result Scalarization: <1 x ty> -> ty.
   void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
   SDValue ScalarizeVecRes_BinOp(SDNode *N);
+  SDValue ScalarizeVecRes_ShiftOp(SDNode *N);
   SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
 
   SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 35eb7cd7db5..5f15fa506d3 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -91,6 +91,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::UDIV:
   case ISD::UREM:
   case ISD::XOR:  R = ScalarizeVecRes_BinOp(N); break;
+
+  case ISD::SHL:
+  case ISD::SRA:
+  case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break;
   }
 
   // If R is null, the sub-method took care of registering the result.
@@ -104,6 +108,17 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
   return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
 }
 
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
+  SDValue LHS = GetScalarizedVector(N->getOperand(0));
+  SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
+  if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
+    ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
+  else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
+    ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+
+  return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
+}
+
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
   MVT NewVT = N->getValueType(0).getVectorElementType();
   return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
@@ -392,6 +407,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR:
+  case ISD::SHL:
+  case ISD::SRA:
+  case ISD::SRL: 
   case ISD::UREM:
   case ISD::SREM:
   case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
diff --git a/test/CodeGen/X86/vshift_scalar.ll b/test/CodeGen/X86/vshift_scalar.ll
new file mode 100644
index 00000000000..8895cdf8aff
--- /dev/null
+++ b/test/CodeGen/X86/vshift_scalar.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc
+
+; Legalization test that requires scalarizing a vector.
+
+define void @update(<1 x i32> %val, <1 x i32>* %dst) nounwind {
+entry:
+	%shl = shl <1 x i32> %val, < i32 2>
+	%shr = ashr <1 x i32> %val, < i32 4>
+	store <1 x i32> %shr, <1 x i32>* %dst
+	ret void
+}
diff --git a/test/CodeGen/X86/vshift_split2.ll b/test/CodeGen/X86/vshift_split2.ll
new file mode 100644
index 00000000000..356e0fd1a64
--- /dev/null
+++ b/test/CodeGen/X86/vshift_split2.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc
+
+; Legalization example that requires splitting a large vector into smaller pieces.
+
+define void @update(<8 x i32> %val, <8 x i32>* %dst) nounwind {
+entry:
+	%shl = shl <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
+	%shr = ashr <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
+	store <8 x i32> %shr, <8 x i32>* %dst
+	ret void
+}