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Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
b48ef3a3ec
commit
93b3eff623
@ -683,8 +683,8 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
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InstrItinClass itin_upd, bits<6> T1Enc,
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bit L_bit, string baseOpc> {
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def IA :
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T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
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T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
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T1Encoding<T1Enc> {
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bits<3> Rn;
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bits<8> regs;
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@ -696,7 +696,7 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
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InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
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"$Rn = $wb", itin_upd>,
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PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
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GPR:$Rn, pred:$p, reglist:$regs)> {
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tGPR:$Rn, pred:$p, reglist:$regs)> {
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let Size = 2;
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let OutOperandList = (outs GPR:$wb);
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let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
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@ -720,6 +720,11 @@ defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
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} // neverHasSideEffects
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def : InstAlias<"ldm${p} $Rn!, $regs",
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(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
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Requires<[IsThumb, IsThumb1Only]>;
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let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
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def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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IIC_iPop,
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@ -2988,6 +2988,29 @@ validateInstruction(MCInst &Inst,
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"bitfield width must be in range [1,32-lsb]");
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return false;
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}
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case ARM::tLDMIA: {
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// Thumb LDM instructions are writeback iff the base register is not
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// in the register list.
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unsigned Rn = Inst.getOperand(0).getReg();
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bool doesWriteback = true;
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for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
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unsigned Reg = Inst.getOperand(i).getReg();
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if (Reg == Rn)
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doesWriteback = false;
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// Anything other than a low register isn't legal here.
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if (getARMRegisterNumbering(Reg) > 7)
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return Error(Operands[4]->getStartLoc(),
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"registers must be in range r0-r7");
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}
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// If we should have writeback, then there should be a '!' token.
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if (doesWriteback &&
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(!static_cast<ARMOperand*>(Operands[3])->isToken() ||
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static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
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return Error(Operands[2]->getStartLoc(),
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"writeback operator '!' expected");
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break;
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}
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}
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return false;
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@ -155,9 +155,9 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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if (Opcode == ARM::tLDMIA)
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O << "\tldmia";
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O << "\tldm";
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else if (Opcode == ARM::tSTMIA)
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O << "\tstmia";
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O << "\tstm";
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else
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llvm_unreachable("Unknown opcode!");
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@ -15,7 +15,7 @@ define i32 @t1() {
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define i32 @t2() {
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; CHECK: t2:
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; CHECK: push {r7, lr}
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; CHECK: ldmia
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; CHECK: ldm
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; CHECK: pop {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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@ -162,3 +162,15 @@ _func:
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eors r4, r5
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@ CHECK: eors r4, r5 @ encoding: [0x6c,0x40]
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@------------------------------------------------------------------------------
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@ LDM
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@------------------------------------------------------------------------------
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ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
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ldm r2!, {r1, r3, r4, r5, r7}
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ldm r1, {r1}
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@ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
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@ CHECK: ldm r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
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@ CHECK: ldm r1, {r1} @ encoding: [0x02,0xc9]
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@ -39,3 +39,13 @@ error: invalid operand for instruction
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error: invalid operand for instruction
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bkpt #-1
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^
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@ Invalid writeback and register lists for LDM
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: ldm r2!, {r5, r8}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' expected
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@ CHECK-ERRORS: ldm r2, {r5, r7}
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@ CHECK-ERRORS: ^
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@ -27,7 +27,7 @@
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# CHECK: cmn.w r0, #31
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0x10 0xf1 0x1f 0x0f
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# CHECK: ldmia r0!, {r1}
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# CHECK: ldm r0!, {r1}
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0x02 0xc8
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# CHECK: ldr r5, #432
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@ -112,7 +112,7 @@
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# CHECK: lsleq r1, r0, #28
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0x01 0x07
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# CHECK: stmiane r0!, {r1, r2, r3}
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# CHECK: stmne r0!, {r1, r2, r3}
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0x0e 0xc0
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# IT block end
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@ -146,13 +146,13 @@
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# CHECK: stmdb.w sp, {r0, r2, r3, r8, r11, lr}
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0x0d 0xe9 0x0d 0x49
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# CHECK: stmia r5!, {r0, r1, r2, r3, r4}
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# CHECK: stm r5!, {r0, r1, r2, r3, r4}
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0x1f 0xc5
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# CHECK: ldmia r5, {r0, r1, r2, r3, r4, r5}
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# CHECK: ldm r5, {r0, r1, r2, r3, r4, r5}
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0x3f 0xcd
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# CHECK: ldmia r5!, {r0, r1, r2, r3, r4}
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# CHECK: ldm r5!, {r0, r1, r2, r3, r4}
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0x1f 0xcd
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# CHECK: addw r0, pc, #1050
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