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[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.
Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.
** Context **
Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.
** Motivating Example **
Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
%ld = load i8* %addr1
%zextld = zext i8 %ld to i32
%ld2 = load i32* %addr2
%add = add nsw i32 %ld2, %zextld
%sextadd = sext i32 %add to i64
%zexta = zext i8 %a to i32
%addza = add nsw i32 %zexta, %zextld
%sextaddza = sext i32 %addza to i64
%addb = add nsw i32 %b, %zextld
%sextaddb = sext i32 %addb to i64
call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
ret void
}
As it is, this IR generates the following assembly on x86_64:
[...]
movzbl (%rdi), %eax # zero-extended load
movl (%rsi), %es # plain load
addl %eax, %esi # 32-bit add
movslq %esi, %rdi # sign extend the result of add
movzbl %dl, %edx # zero extend the first argument
addl %eax, %edx # 32-bit add
movslq %edx, %rsi # sign extend the result of add
addl %eax, %ecx # 32-bit add
movslq %ecx, %rdx # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.
Now, by promoting the additions to form more extended loads we would generate:
[...]
movzbl (%rdi), %eax # zero-extended load
movslq (%rsi), %rdi # sign-extended load
addq %rax, %rdi # 64-bit add
movzbl %dl, %esi # zero extend the first argument
addq %rax, %rsi # 64-bit add
movslq %ecx, %rdx # sign extend the second argument
addq %rax, %rdx # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.
This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.
Note: The throughput numbers are similar on Sandy Bridge and Haswell.
** Proposed Solution **
To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))
The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.
** Performance **
Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar: ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%
The results are consistent for both O3 and Os.
<rdar://problem/18310086>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
parent
6e5ad1fc76
commit
93b6e016b1
@ -264,6 +264,11 @@ public:
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return MaskAndBranchFoldingIsLegal;
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}
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/// \brief Return true if the target wants to use the optimization that
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/// turns ext(promotableInst1(...(promotableInstN(load)))) into
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/// promotedInst1(...(promotedInstN(ext(load)))).
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bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
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/// Return true if the target can combine store(extractelement VectorTy,
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/// Idx).
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/// \p Cost[out] gives the cost of that transformation when this is true.
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@ -1954,6 +1959,9 @@ protected:
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/// a mask of a single bit, a compare, and a branch into a single instruction.
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bool MaskAndBranchFoldingIsLegal;
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/// \see enableExtLdPromotion.
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bool EnableExtLdPromotion;
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protected:
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/// Return true if the value types that can be represented by the specified
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/// register class are all legal.
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@ -91,6 +91,16 @@ static cl::opt<bool> StressStoreExtract(
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"stress-cgp-store-extract", cl::Hidden, cl::init(false),
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cl::desc("Stress test store(extract) optimizations in CodeGenPrepare"));
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static cl::opt<bool> DisableExtLdPromotion(
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"disable-cgp-ext-ld-promotion", cl::Hidden, cl::init(false),
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cl::desc("Disable ext(promotable(ld)) -> promoted(ext(ld)) optimization in "
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"CodeGenPrepare"));
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static cl::opt<bool> StressExtLdPromotion(
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"stress-cgp-ext-ld-promotion", cl::Hidden, cl::init(false),
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cl::desc("Stress test ext(promotable(ld)) -> promoted(ext(ld)) "
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"optimization in CodeGenPrepare"));
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namespace {
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typedef SmallPtrSet<Instruction *, 16> SetOfInstrs;
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struct TypeIsSExt {
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@ -99,6 +109,7 @@ struct TypeIsSExt {
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TypeIsSExt(Type *Ty, bool IsSExt) : Ty(Ty), IsSExt(IsSExt) {}
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};
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typedef DenseMap<Instruction *, TypeIsSExt> InstrToOrigTy;
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class TypePromotionTransaction;
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class CodeGenPrepare : public FunctionPass {
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/// TLI - Keep a pointer of a TargetLowering to consult for determining
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@ -158,7 +169,7 @@ typedef DenseMap<Instruction *, TypeIsSExt> InstrToOrigTy;
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bool OptimizeMemoryInst(Instruction *I, Value *Addr, Type *AccessTy);
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bool OptimizeInlineAsmInst(CallInst *CS);
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bool OptimizeCallInst(CallInst *CI);
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bool MoveExtToFormExtLoad(Instruction *I);
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bool MoveExtToFormExtLoad(Instruction *&I);
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bool OptimizeExtUses(Instruction *I);
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bool OptimizeSelectInst(SelectInst *SI);
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bool OptimizeShuffleVectorInst(ShuffleVectorInst *SI);
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@ -166,6 +177,10 @@ typedef DenseMap<Instruction *, TypeIsSExt> InstrToOrigTy;
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bool DupRetToEnableTailCallOpts(BasicBlock *BB);
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bool PlaceDbgValues(Function &F);
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bool sinkAndCmp(Function &F);
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bool ExtLdPromotion(TypePromotionTransaction &TPT, LoadInst *&LI,
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Instruction *&Inst,
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const SmallVectorImpl<Instruction *> &Exts,
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unsigned CreatedInst);
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bool splitBranchCondition(Function &F);
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};
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}
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@ -1722,6 +1737,23 @@ static bool MightBeFoldableInst(Instruction *I) {
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}
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}
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/// \brief Check whether or not \p Val is a legal instruction for \p TLI.
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/// \note \p Val is assumed to be the product of some type promotion.
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/// Therefore if \p Val has an undefined state in \p TLI, this is assumed
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/// to be legal, as the non-promoted value would have had the same state.
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static bool isPromotedInstructionLegal(const TargetLowering &TLI, Value *Val) {
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Instruction *PromotedInst = dyn_cast<Instruction>(Val);
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if (!PromotedInst)
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return false;
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int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode());
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// If the ISDOpcode is undefined, it was undefined before the promotion.
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if (!ISDOpcode)
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return true;
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// Otherwise, check if the promoted instruction is legal or not.
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return TLI.isOperationLegalOrCustom(
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ISDOpcode, TLI.getValueType(PromotedInst->getType()));
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}
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/// \brief Hepler class to perform type promotion.
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class TypePromotionHelper {
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/// \brief Utility function to check whether or not a sign or zero extension
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@ -1751,46 +1783,59 @@ class TypePromotionHelper {
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/// \p PromotedInsts maps the instructions to their type before promotion.
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/// \p CreatedInsts[out] contains how many non-free instructions have been
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/// created to promote the operand of Ext.
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/// Newly added extensions are inserted in \p Exts.
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/// Newly added truncates are inserted in \p Truncs.
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/// Should never be called directly.
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/// \return The promoted value which is used instead of Ext.
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static Value *promoteOperandForTruncAndAnyExt(Instruction *Ext,
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TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts);
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static Value *promoteOperandForTruncAndAnyExt(
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Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs);
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/// \brief Utility function to promote the operand of \p Ext when this
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/// operand is promotable and is not a supported trunc or sext.
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/// \p PromotedInsts maps the instructions to their type before promotion.
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/// \p CreatedInsts[out] contains how many non-free instructions have been
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/// created to promote the operand of Ext.
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/// Newly added extensions are inserted in \p Exts.
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/// Newly added truncates are inserted in \p Truncs.
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/// Should never be called directly.
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/// \return The promoted value which is used instead of Ext.
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static Value *promoteOperandForOther(Instruction *Ext,
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TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts, bool IsSExt);
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static Value *
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promoteOperandForOther(Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs, bool IsSExt);
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/// \see promoteOperandForOther.
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static Value *signExtendOperandForOther(Instruction *Ext,
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TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts) {
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return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInsts, true);
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static Value *
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signExtendOperandForOther(Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs) {
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return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInsts, Exts,
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Truncs, true);
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}
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/// \see promoteOperandForOther.
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static Value *zeroExtendOperandForOther(Instruction *Ext,
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TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts) {
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return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInsts, false);
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static Value *
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zeroExtendOperandForOther(Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs) {
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return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInsts, Exts,
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Truncs, false);
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}
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public:
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/// Type for the utility function that promotes the operand of Ext.
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typedef Value *(*Action)(Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts,
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unsigned &CreatedInsts);
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs);
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/// \brief Given a sign/zero extend instruction \p Ext, return the approriate
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/// action to promote the operand of \p Ext instead of using Ext.
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/// \return NULL if no promotable action is possible with the current
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@ -1834,8 +1879,9 @@ bool TypePromotionHelper::canGetThrough(const Instruction *Inst,
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// Check if we can use this operand in the extension.
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// If the type is larger than the result type of the extension,
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// we cannot.
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if (OpndVal->getType()->getIntegerBitWidth() >
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ConsideredExtType->getIntegerBitWidth())
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if (!OpndVal->getType()->isIntegerTy() ||
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OpndVal->getType()->getIntegerBitWidth() >
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ConsideredExtType->getIntegerBitWidth())
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return false;
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// If the operand of the truncate is not an instruction, we will not have
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@ -1900,7 +1946,9 @@ TypePromotionHelper::Action TypePromotionHelper::getAction(
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Value *TypePromotionHelper::promoteOperandForTruncAndAnyExt(
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llvm::Instruction *SExt, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts) {
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs) {
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// By construction, the operand of SExt is an instruction. Otherwise we cannot
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// get through it and this method should not be called.
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Instruction *SExtOpnd = cast<Instruction>(SExt->getOperand(0));
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@ -1926,8 +1974,11 @@ Value *TypePromotionHelper::promoteOperandForTruncAndAnyExt(
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// Check if the extension is still needed.
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Instruction *ExtInst = dyn_cast<Instruction>(ExtVal);
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if (!ExtInst || ExtInst->getType() != ExtInst->getOperand(0)->getType())
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if (!ExtInst || ExtInst->getType() != ExtInst->getOperand(0)->getType()) {
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if (ExtInst && Exts)
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Exts->push_back(ExtInst);
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return ExtVal;
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}
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// At this point we have: ext ty opnd to ty.
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// Reassign the uses of ExtInst to the opnd and remove ExtInst.
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@ -1938,7 +1989,9 @@ Value *TypePromotionHelper::promoteOperandForTruncAndAnyExt(
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Value *TypePromotionHelper::promoteOperandForOther(
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Instruction *Ext, TypePromotionTransaction &TPT,
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts, bool IsSExt) {
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InstrToOrigTy &PromotedInsts, unsigned &CreatedInsts,
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SmallVectorImpl<Instruction *> *Exts,
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SmallVectorImpl<Instruction *> *Truncs, bool IsSExt) {
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// By construction, the operand of Ext is an instruction. Otherwise we cannot
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// get through it and this method should not be called.
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Instruction *ExtOpnd = cast<Instruction>(Ext->getOperand(0));
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@ -1953,6 +2006,8 @@ Value *TypePromotionHelper::promoteOperandForOther(
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ITrunc->removeFromParent();
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// Insert it just after the definition.
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ITrunc->insertAfter(ExtOpnd);
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if (Truncs)
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Truncs->push_back(ITrunc);
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}
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TPT.replaceAllUsesWith(ExtOpnd, Trunc);
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@ -2013,7 +2068,8 @@ Value *TypePromotionHelper::promoteOperandForOther(
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: TPT.createZExt(Ext, Opnd, Ext->getType()));
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++CreatedInsts;
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}
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if (Exts)
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Exts->push_back(ExtForOpnd);
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TPT.setOperand(ExtForOpnd, 0, Opnd);
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// Move the sign extension before the insertion point.
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@ -2051,16 +2107,7 @@ AddressingModeMatcher::IsPromotionProfitable(unsigned MatchedSize,
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// The promotion is neutral but it may help folding the sign extension in
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// loads for instance.
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// Check that we did not create an illegal instruction.
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Instruction *PromotedInst = dyn_cast<Instruction>(PromotedOperand);
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if (!PromotedInst)
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return false;
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int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode());
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// If the ISDOpcode is undefined, it was undefined before the promotion.
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if (!ISDOpcode)
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return true;
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// Otherwise, check if the promoted instruction is legal or not.
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return TLI.isOperationLegalOrCustom(
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ISDOpcode, TLI.getValueType(PromotedInst->getType()));
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return isPromotedInstructionLegal(TLI, PromotedOperand);
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}
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/// MatchOperationAddr - Given an instruction or constant expr, see if we can
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@ -2254,7 +2301,8 @@ bool AddressingModeMatcher::MatchOperationAddr(User *AddrInst, unsigned Opcode,
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TypePromotionTransaction::ConstRestorationPt LastKnownGood =
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TPT.getRestorationPoint();
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unsigned CreatedInsts = 0;
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Value *PromotedOperand = TPH(Ext, TPT, PromotedInsts, CreatedInsts);
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Value *PromotedOperand =
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TPH(Ext, TPT, PromotedInsts, CreatedInsts, nullptr, nullptr);
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// SExt has been moved away.
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// Thus either it will be rematched later in the recursive calls or it is
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// gone. Anyway, we must not fold it into the addressing mode at this point.
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@ -2953,17 +3001,172 @@ bool CodeGenPrepare::OptimizeInlineAsmInst(CallInst *CS) {
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return MadeChange;
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}
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/// \brief Check if all the uses of \p Inst are equivalent (or free) zero or
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/// sign extensions.
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static bool hasSameExtUse(Instruction *Inst, const TargetLowering &TLI) {
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assert(!Inst->use_empty() && "Input must have at least one use");
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const Instruction *FirstUser = cast<Instruction>(*Inst->user_begin());
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bool IsSExt = isa<SExtInst>(FirstUser);
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Type *ExtTy = FirstUser->getType();
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for (const User *U : Inst->users()) {
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const Instruction *UI = cast<Instruction>(U);
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if ((IsSExt && !isa<SExtInst>(UI)) || (!IsSExt && !isa<ZExtInst>(UI)))
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return false;
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Type *CurTy = UI->getType();
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// Same input and output types: Same instruction after CSE.
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if (CurTy == ExtTy)
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continue;
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// If IsSExt is true, we are in this situation:
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// a = Inst
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// b = sext ty1 a to ty2
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// c = sext ty1 a to ty3
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// Assuming ty2 is shorter than ty3, this could be turned into:
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// a = Inst
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// b = sext ty1 a to ty2
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// c = sext ty2 b to ty3
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// However, the last sext is not free.
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if (IsSExt)
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return false;
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// This is a ZExt, maybe this is free to extend from one type to another.
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// In that case, we would not account for a different use.
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Type *NarrowTy;
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Type *LargeTy;
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if (ExtTy->getScalarType()->getIntegerBitWidth() >
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CurTy->getScalarType()->getIntegerBitWidth()) {
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NarrowTy = CurTy;
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LargeTy = ExtTy;
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} else {
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NarrowTy = ExtTy;
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LargeTy = CurTy;
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}
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if (!TLI.isZExtFree(NarrowTy, LargeTy))
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return false;
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}
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// All uses are the same or can be derived from one another for free.
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return true;
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}
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/// \brief Try to form ExtLd by promoting \p Exts until they reach a
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/// load instruction.
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/// If an ext(load) can be formed, it is returned via \p LI for the load
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/// and \p Inst for the extension.
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/// Otherwise LI == nullptr and Inst == nullptr.
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/// When some promotion happened, \p TPT contains the proper state to
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/// revert them.
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///
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/// \return true when promoting was necessary to expose the ext(load)
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/// opportunity, false otherwise.
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///
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/// Example:
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/// \code
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/// %ld = load i32* %addr
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/// %add = add nuw i32 %ld, 4
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/// %zext = zext i32 %add to i64
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/// \endcode
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/// =>
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/// \code
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/// %ld = load i32* %addr
|
||||
/// %zext = zext i32 %ld to i64
|
||||
/// %add = add nuw i64 %zext, 4
|
||||
/// \encode
|
||||
/// Thanks to the promotion, we can match zext(load i32*) to i64.
|
||||
bool CodeGenPrepare::ExtLdPromotion(TypePromotionTransaction &TPT,
|
||||
LoadInst *&LI, Instruction *&Inst,
|
||||
const SmallVectorImpl<Instruction *> &Exts,
|
||||
unsigned CreatedInsts = 0) {
|
||||
// Iterate over all the extensions to see if one form an ext(load).
|
||||
for (auto I : Exts) {
|
||||
// Check if we directly have ext(load).
|
||||
if ((LI = dyn_cast<LoadInst>(I->getOperand(0)))) {
|
||||
Inst = I;
|
||||
// No promotion happened here.
|
||||
return false;
|
||||
}
|
||||
// Check whether or not we want to do any promotion.
|
||||
if (!TLI || !TLI->enableExtLdPromotion() || DisableExtLdPromotion)
|
||||
continue;
|
||||
// Get the action to perform the promotion.
|
||||
TypePromotionHelper::Action TPH = TypePromotionHelper::getAction(
|
||||
I, InsertedTruncsSet, *TLI, PromotedInsts);
|
||||
// Check if we can promote.
|
||||
if (!TPH)
|
||||
continue;
|
||||
// Save the current state.
|
||||
TypePromotionTransaction::ConstRestorationPt LastKnownGood =
|
||||
TPT.getRestorationPoint();
|
||||
SmallVector<Instruction *, 4> NewExts;
|
||||
unsigned NewCreatedInsts = 0;
|
||||
// Promote.
|
||||
Value *PromotedVal =
|
||||
TPH(I, TPT, PromotedInsts, NewCreatedInsts, &NewExts, nullptr);
|
||||
assert(PromotedVal &&
|
||||
"TypePromotionHelper should have filtered out those cases");
|
||||
|
||||
// We would be able to merge only one extension in a load.
|
||||
// Therefore, if we have more than 1 new extension we heuristically
|
||||
// cut this search path, because it means we degrade the code quality.
|
||||
// With exactly 2, the transformation is neutral, because we will merge
|
||||
// one extension but leave one. However, we optimistically keep going,
|
||||
// because the new extension may be removed too.
|
||||
unsigned TotalCreatedInsts = CreatedInsts + NewCreatedInsts;
|
||||
if (!StressExtLdPromotion &&
|
||||
(TotalCreatedInsts > 1 ||
|
||||
!isPromotedInstructionLegal(*TLI, PromotedVal))) {
|
||||
// The promotion is not profitable, rollback to the previous state.
|
||||
TPT.rollback(LastKnownGood);
|
||||
continue;
|
||||
}
|
||||
// The promotion is profitable.
|
||||
// Check if it exposes an ext(load).
|
||||
(void)ExtLdPromotion(TPT, LI, Inst, NewExts, TotalCreatedInsts);
|
||||
if (LI && (StressExtLdPromotion || NewCreatedInsts == 0 ||
|
||||
// If we have created a new extension, i.e., now we have two
|
||||
// extensions. We must make sure one of them is merged with
|
||||
// the load, otherwise we may degrade the code quality.
|
||||
(LI->hasOneUse() || hasSameExtUse(LI, *TLI))))
|
||||
// Promotion happened.
|
||||
return true;
|
||||
// If this does not help to expose an ext(load) then, rollback.
|
||||
TPT.rollback(LastKnownGood);
|
||||
}
|
||||
// None of the extension can form an ext(load).
|
||||
LI = nullptr;
|
||||
Inst = nullptr;
|
||||
return false;
|
||||
}
|
||||
|
||||
/// MoveExtToFormExtLoad - Move a zext or sext fed by a load into the same
|
||||
/// basic block as the load, unless conditions are unfavorable. This allows
|
||||
/// SelectionDAG to fold the extend into the load.
|
||||
/// \p I[in/out] the extension may be modified during the process if some
|
||||
/// promotions apply.
|
||||
///
|
||||
bool CodeGenPrepare::MoveExtToFormExtLoad(Instruction *I) {
|
||||
bool CodeGenPrepare::MoveExtToFormExtLoad(Instruction *&I) {
|
||||
// Try to promote a chain of computation if it allows to form
|
||||
// an extended load.
|
||||
TypePromotionTransaction TPT;
|
||||
TypePromotionTransaction::ConstRestorationPt LastKnownGood =
|
||||
TPT.getRestorationPoint();
|
||||
SmallVector<Instruction *, 1> Exts;
|
||||
Exts.push_back(I);
|
||||
// Look for a load being extended.
|
||||
LoadInst *LI = dyn_cast<LoadInst>(I->getOperand(0));
|
||||
if (!LI) return false;
|
||||
LoadInst *LI = nullptr;
|
||||
Instruction *OldExt = I;
|
||||
bool HasPromoted = ExtLdPromotion(TPT, LI, I, Exts);
|
||||
if (!LI || !I) {
|
||||
assert(!HasPromoted && !LI && "If we did not match any load instruction "
|
||||
"the code must remain the same");
|
||||
I = OldExt;
|
||||
return false;
|
||||
}
|
||||
|
||||
// If they're already in the same block, there's nothing to do.
|
||||
if (LI->getParent() == I->getParent())
|
||||
// Make the cheap checks first if we did not promote.
|
||||
// If we promoted, we need to check if it is indeed profitable.
|
||||
if (!HasPromoted && LI->getParent() == I->getParent())
|
||||
return false;
|
||||
|
||||
EVT VT = TLI->getValueType(I->getType());
|
||||
@ -2973,8 +3176,11 @@ bool CodeGenPrepare::MoveExtToFormExtLoad(Instruction *I) {
|
||||
// isn't worthwhile.
|
||||
if (!LI->hasOneUse() && TLI &&
|
||||
(TLI->isTypeLegal(LoadVT) || !TLI->isTypeLegal(VT)) &&
|
||||
!TLI->isTruncateFree(I->getType(), LI->getType()))
|
||||
!TLI->isTruncateFree(I->getType(), LI->getType())) {
|
||||
I = OldExt;
|
||||
TPT.rollback(LastKnownGood);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Check whether the target supports casts folded into loads.
|
||||
unsigned LType;
|
||||
@ -2984,11 +3190,15 @@ bool CodeGenPrepare::MoveExtToFormExtLoad(Instruction *I) {
|
||||
assert(isa<SExtInst>(I) && "Unexpected ext type!");
|
||||
LType = ISD::SEXTLOAD;
|
||||
}
|
||||
if (TLI && !TLI->isLoadExtLegal(LType, LoadVT))
|
||||
if (TLI && !TLI->isLoadExtLegal(LType, LoadVT)) {
|
||||
I = OldExt;
|
||||
TPT.rollback(LastKnownGood);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Move the extend into the same block as the load, so that SelectionDAG
|
||||
// can fold it.
|
||||
TPT.commit();
|
||||
I->removeFromParent();
|
||||
I->insertAfter(LI);
|
||||
++NumExtsMoved;
|
||||
|
||||
@ -714,6 +714,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
|
||||
JumpIsExpensive = false;
|
||||
PredictableSelectIsExpensive = false;
|
||||
MaskAndBranchFoldingIsLegal = false;
|
||||
EnableExtLdPromotion = false;
|
||||
HasFloatingPointExceptions = true;
|
||||
StackPointerRegisterToSaveRestore = 0;
|
||||
ExceptionPointerRegister = 0;
|
||||
|
||||
@ -1689,7 +1689,7 @@ void X86TargetLowering::resetOperationActions() {
|
||||
|
||||
// Predictable cmov don't hurt on atom because it's in-order.
|
||||
PredictableSelectIsExpensive = !Subtarget->isAtom();
|
||||
|
||||
EnableExtLdPromotion = true;
|
||||
setPrefFunctionAlignment(4); // 2^4 bytes.
|
||||
|
||||
verifyIntrinsicTables();
|
||||
|
||||
@ -1,12 +1,21 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s
|
||||
; rdar://7304838
|
||||
; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
|
||||
; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
|
||||
; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
|
||||
|
||||
; rdar://7304838
|
||||
; CodeGenPrepare should move the zext into the block with the load
|
||||
; so that SelectionDAG can select it with the load.
|
||||
|
||||
;
|
||||
; CHECK-LABEL: foo:
|
||||
; CHECK: movsbl ({{%rdi|%rcx}}), %eax
|
||||
|
||||
;
|
||||
; OPTALL-LABEL: @foo
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; OPTALL: store i32 [[ZEXT]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @foo(i8* %p, i32* %q) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
@ -19,3 +28,298 @@ true:
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a zextload is an operation with only one
|
||||
; argument to explicitly extend is in the the way.
|
||||
; OPTALL-LABEL: @promoteOneArg
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
|
||||
; Make sure the operation is not promoted when the promotion pass is disabled.
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteOneArg(i8* %p, i32* %q) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%add = add nuw i8 %t, 2
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = zext i8 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a sextload is an operation with only one
|
||||
; argument to explicitly extend is in the the way.
|
||||
; Version with sext.
|
||||
; OPTALL-LABEL: @promoteOneArgSExt
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
|
||||
; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteOneArgSExt(i8* %p, i32* %q) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%add = add nsw i8 %t, 2
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = sext i8 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a zextload is an operation with two
|
||||
; arguments to explicitly extend is in the the way.
|
||||
; Extending %add will create two extensions:
|
||||
; 1. One for %b.
|
||||
; 2. One for %t.
|
||||
; #1 will not be removed as we do not know anything about %b.
|
||||
; #2 may not be merged with the load because %t is used in a comparison.
|
||||
; Since two extensions may be emitted in the end instead of one before the
|
||||
; transformation, the regular heuristic does not apply the optimization.
|
||||
;
|
||||
; OPTALL-LABEL: @promoteTwoArgZext
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
;
|
||||
; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
|
||||
; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
|
||||
;
|
||||
; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
|
||||
; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
|
||||
;
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
|
||||
;
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%add = add nuw i8 %t, %b
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = zext i8 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a sextload is an operation with two
|
||||
; arguments to explicitly extend is in the the way.
|
||||
; Version with sext.
|
||||
; OPTALL-LABEL: @promoteTwoArgSExt
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
;
|
||||
; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
|
||||
; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
|
||||
; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]]
|
||||
;
|
||||
; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
|
||||
; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
|
||||
;
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%add = add nsw i8 %t, %b
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = sext i8 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we do not a zextload if we need to introduce more than
|
||||
; one additional extension.
|
||||
; OPTALL-LABEL: @promoteThreeArgZext
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
;
|
||||
; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
|
||||
; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
|
||||
; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32
|
||||
; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
|
||||
;
|
||||
; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
|
||||
; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c
|
||||
; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
|
||||
;
|
||||
; DISABLE: add nuw i8
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
|
||||
;
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%tmp = add nuw i8 %t, %b
|
||||
%add = add nuw i8 %tmp, %c
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = zext i8 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a zextload after promoting and merging
|
||||
; two extensions.
|
||||
; OPTALL-LABEL: @promoteMergeExtArgZExt
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
;
|
||||
; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
|
||||
; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
|
||||
;
|
||||
; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
|
||||
; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
|
||||
; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
|
||||
;
|
||||
; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
|
||||
;
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%ext = zext i8 %t to i16
|
||||
%add = add nuw i16 %ext, %b
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = zext i16 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to form a sextload after promoting and merging
|
||||
; two extensions.
|
||||
; Version with sext.
|
||||
; OPTALL-LABEL: @promoteMergeExtArgSExt
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %p
|
||||
;
|
||||
; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
||||
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
|
||||
; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]]
|
||||
;
|
||||
; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
|
||||
; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
|
||||
; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
|
||||
;
|
||||
; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
|
||||
; OPTALL: store i32 [[RES]], i32* %q
|
||||
; OPTALL: ret
|
||||
define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) {
|
||||
entry:
|
||||
%t = load i8* %p
|
||||
%ext = zext i8 %t to i16
|
||||
%add = add nsw i16 %ext, %b
|
||||
%a = icmp slt i8 %t, 20
|
||||
br i1 %a, label %true, label %false
|
||||
true:
|
||||
%s = sext i16 %add to i32
|
||||
store i32 %s, i32* %q
|
||||
ret void
|
||||
false:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that we manage to catch all the extload opportunities that are exposed
|
||||
; by the different iterations of codegen prepare.
|
||||
; Moreover, check that we do not promote more than we need to.
|
||||
; Here is what is happening in this test (not necessarly in this order):
|
||||
; 1. We try to promote the operand of %sextadd.
|
||||
; a. This creates one sext of %ld2 and one of %zextld
|
||||
; b. The sext of %ld2 can be combine with %ld2, so we remove one sext but
|
||||
; introduced one. This is fine with the current heuristic: neutral.
|
||||
; => We have one zext of %zextld left and we created one sext of %ld2.
|
||||
; 2. We try to promote the operand of %sextaddza.
|
||||
; a. This creates one sext of %zexta and one of %zextld
|
||||
; b. The sext of %zexta does not lead to any load, it stays here, even if it
|
||||
; could have been combine with the zext of %a.
|
||||
; c. The sext of %zextld leads to %ld and can be combined with it. This is
|
||||
; done by promoting %zextld. This is fine with the current heuristic:
|
||||
; neutral.
|
||||
; => We have created a new zext of %ld and we created one sext of %zexta.
|
||||
; 3. We try to promote the operand of %sextaddb.
|
||||
; a. This creates one sext of %b and one of %zextld
|
||||
; b. The sext of %b is a dead-end, nothing to be done.
|
||||
; c. Same thing as 2.c. happens.
|
||||
; => We have created a new zext of %ld and we created one sext of %b.
|
||||
; 4. We try to promote the operand of the zext of %zextld introduced in #1.
|
||||
; a. Same thing as 2.c. happens.
|
||||
; b. %zextld does not have any other uses. It is dead coded.
|
||||
; => We have created a new zext of %ld and we removed a zext of %zextld and
|
||||
; a zext of %ld.
|
||||
; Currently we do not try to reuse existing extensions, so in the end we have
|
||||
; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
|
||||
;
|
||||
; OPTALL-LABEL: @severalPromotions
|
||||
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8* %addr1
|
||||
; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
||||
; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
||||
; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
||||
; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32* %addr2
|
||||
; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
|
||||
; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]]
|
||||
; We do not combine this one: see 2.b.
|
||||
; OPT-NEXT: [[ZEXTA:%[a-zA-Z_0-9-]+]] = zext i8 %a to i32
|
||||
; OPT-NEXT: [[SEXTZEXTA:%[a-zA-Z_0-9-]+]] = sext i32 [[ZEXTA]] to i64
|
||||
; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTZEXTA]], [[ZEXTLD1_3]]
|
||||
; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
||||
; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_2]]
|
||||
;
|
||||
; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32
|
||||
; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
|
||||
; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32
|
||||
; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDZA]] to i64
|
||||
; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32
|
||||
; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDB]] to i64
|
||||
;
|
||||
; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
|
||||
; OPTALL: ret
|
||||
define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
|
||||
%ld = load i8* %addr1
|
||||
%zextld = zext i8 %ld to i32
|
||||
%ld2 = load i32* %addr2
|
||||
%add = add nsw i32 %ld2, %zextld
|
||||
%sextadd = sext i32 %add to i64
|
||||
%zexta = zext i8 %a to i32
|
||||
%addza = add nsw i32 %zexta, %zextld
|
||||
%sextaddza = sext i32 %addza to i64
|
||||
%addb = add nsw i32 %b, %zextld
|
||||
%sextaddb = sext i32 %addb to i64
|
||||
call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @dummy(i64, i64, i64)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user