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https://github.com/c64scene-ar/llvm-6502.git
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MIPS DSP: other miscellaneous instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
284c1004f7
commit
93ba059e48
@ -141,6 +141,21 @@ class SHLL_QB_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b010011;
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}
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// LX sub-class format.
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class LX_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> base;
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bits<5> index;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = base;
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let Inst{20-16} = index;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b001010;
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}
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// ADDUH.QB sub-class format.
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class ADDUH_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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@ -156,6 +171,21 @@ class ADDUH_QB_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b011000;
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}
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// APPEND sub-class format.
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class APPEND_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b110001;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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@ -243,6 +273,18 @@ class RDDSP_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b111000;
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}
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class WRDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-11} = mask;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class BPOSGE32_FMT<bits<5> op> : DSPInst {
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bits<16> offset;
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@ -252,3 +294,16 @@ class BPOSGE32_FMT<bits<5> op> : DSPInst {
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let Inst{20-16} = op;
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let Inst{15-0} = offset;
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}
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// INSV sub-class format.
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class INSV_FMT<bits<6> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-6} = 0;
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let Inst{5-0} = op;
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}
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@ -179,7 +179,11 @@ class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
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class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
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class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
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class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
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class LWX_ENC : LX_FMT<0b00000>;
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class LHX_ENC : LX_FMT<0b00100>;
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class LBUX_ENC : LX_FMT<0b00110>;
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class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
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class INSV_ENC : INSV_FMT<0b001100>;
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
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@ -198,6 +202,7 @@ class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
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class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
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class RDDSP_ENC : RDDSP_FMT<0b10010>;
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class WRDSP_ENC : WRDSP_FMT<0b10011>;
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class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
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class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
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class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
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@ -241,6 +246,9 @@ class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
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class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
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class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
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class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
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class APPEND_ENC : APPEND_FMT<0b00000>;
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class BALIGN_ENC : APPEND_FMT<0b10000>;
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class PREPEND_ENC : APPEND_FMT<0b00001>;
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// Instruction desc.
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class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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@ -341,6 +349,18 @@ class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<Register> Defs = [DSPCtrl];
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}
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class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rd);
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dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
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string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
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list<dag> Pattern = [(set CPURegs:$rd,
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(OpNode CPURegs:$base, CPURegs:$index))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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bit mayLoad = 1;
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}
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class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCD,
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RegisterClass RCS = RCD, RegisterClass RCT = RCD> {
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@ -352,6 +372,18 @@ class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<Register> Defs = [DSPCtrl];
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}
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class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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SDPatternOperator ImmOp, InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
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list<dag> Pattern = [(set CPURegs:$rt,
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(OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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string Constraints = "$src = $rt";
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}
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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@ -416,6 +448,16 @@ class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<Register> Uses = [DSPCtrl];
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}
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class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
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string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
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list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
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@ -464,6 +506,17 @@ class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
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bit hasDelaySlot = 1;
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}
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class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
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list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
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InstrItinClass Itinerary = itin;
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list<Register> Uses = [DSPCtrl];
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string Constraints = "$src = $rt";
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}
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 1
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//===----------------------------------------------------------------------===//
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@ -777,6 +830,12 @@ class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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ClearDefs, UseDSPCtrl;
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class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
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class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
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class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
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class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
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// Extr
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@ -820,6 +879,10 @@ class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
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class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
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class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
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class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 2
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// Addition/subtraction
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@ -969,6 +1032,16 @@ class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
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class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
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NoItinerary, DSPRegs>, ClearDefs;
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// Misc
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class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
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NoItinerary>, ClearDefs;
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class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
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NoItinerary>, ClearDefs;
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class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
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NoItinerary>, ClearDefs;
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// Pseudos.
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def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
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@ -1061,7 +1134,11 @@ def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
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def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
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def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
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def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
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def LWX : LWX_ENC, LWX_DESC;
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def LHX : LHX_ENC, LHX_DESC;
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def LBUX : LBUX_ENC, LBUX_DESC;
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def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
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def INSV : INSV_ENC, INSV_DESC;
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def EXTP : EXTP_ENC, EXTP_DESC;
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def EXTPV : EXTPV_ENC, EXTPV_DESC;
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def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
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@ -1078,6 +1155,7 @@ def SHILO : SHILO_ENC, SHILO_DESC;
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def SHILOV : SHILOV_ENC, SHILOV_DESC;
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def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
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def RDDSP : RDDSP_ENC, RDDSP_DESC;
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def WRDSP : WRDSP_ENC, WRDSP_DESC;
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// MIPS DSP Rev 2
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let Predicates = [HasDSPR2] in {
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@ -1125,6 +1203,9 @@ def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
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def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
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def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
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def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
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def APPEND : APPEND_ENC, APPEND_DESC;
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def BALIGN : BALIGN_ENC, BALIGN_DESC;
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def PREPEND : PREPEND_ENC, PREPEND_DESC;
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}
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@ -1198,3 +1198,44 @@ entry:
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}
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declare i32 @llvm.mips.bitrev(i32) nounwind readnone
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define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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; CHECK: lbux
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%0 = tail call i32 @llvm.mips.lbux(i8* %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.lbux(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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; CHECK: lhx
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%0 = tail call i32 @llvm.mips.lhx(i8* %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.lhx(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
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entry:
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; CHECK: lwx
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%0 = tail call i32 @llvm.mips.lwx(i8* %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly
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define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {
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entry:
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; CHECK: wrdsp
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tail call void @llvm.mips.wrdsp(i32 %a0, i32 31)
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %0
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}
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declare void @llvm.mips.wrdsp(i32, i32) nounwind
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@ -536,3 +536,33 @@ entry:
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}
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declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone
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define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: append
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%0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)
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ret i32 %0
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}
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declare i32 @llvm.mips.append(i32, i32, i32) nounwind readnone
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define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: balign
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%0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)
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ret i32 %0
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}
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declare i32 @llvm.mips.balign(i32, i32, i32) nounwind readnone
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define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: prepend
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%0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)
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ret i32 %0
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}
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declare i32 @llvm.mips.prepend(i32, i32, i32) nounwind readnone
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