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https://github.com/c64scene-ar/llvm-6502.git
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Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
23bd47c2d6
commit
93c7c449a1
@ -4444,6 +4444,12 @@ bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
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((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
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((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
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return Error(Loc, "immediate shift value out of range");
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// If <ShiftTy> #0, turn it into a no_shift.
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if (Imm == 0)
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St = ARM_AM::lsl;
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// For consistency, treat lsr #32 and asr #32 as having immediate value 0.
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if (Imm == 32)
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Imm = 0;
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Amount = Imm;
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}
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@ -1523,6 +1523,8 @@ DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
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return MCDisassembler::Fail;
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}
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unsigned amt = fieldFromInstruction(Insn, 7, 5);
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if (Opc == ARM_AM::ror && amt == 0)
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Opc = ARM_AM::rrx;
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unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
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Inst.addOperand(MCOperand::CreateImm(imm));
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@ -1564,6 +1566,9 @@ static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
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break;
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}
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if (ShOp == ARM_AM::ror && imm == 0)
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ShOp = ARM_AM::rrx;
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
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@ -29,11 +29,27 @@ using namespace llvm;
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///
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/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
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static unsigned translateShiftImm(unsigned imm) {
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// lsr #32 and asr #32 exist, but should be encoded as a 0.
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assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
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if (imm == 0)
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return 32;
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return imm;
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}
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/// Prints the shift value with an immediate value.
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static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
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unsigned ShImm) {
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if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
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return;
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O << ", ";
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assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
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O << getShiftOpcStr(ShOpc);
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if (ShOpc != ARM_AM::rrx)
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O << " #" << translateShiftImm(ShImm);
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}
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ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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@ -319,10 +335,8 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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<< " #" << ShImm;
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printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
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ARM_AM::getAM2Offset(MO3.getImm()));
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O << "]";
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}
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@ -403,10 +417,8 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< getRegisterName(MO1.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
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<< " #" << ShImm;
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printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
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ARM_AM::getAM2Offset(MO2.getImm()));
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}
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//===--------------------------------------------------------------------===//
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@ -934,6 +934,10 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
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unsigned SBits = getShiftOp(ShOp);
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// While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
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// amount. However, it would be an easy mistake to make so check here.
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assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
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// {16-13} = Rn
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// {12} = isAdd
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// {11-0} = shifter
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76
test/MC/ARM/arm-shift-encoding.s
Normal file
76
test/MC/ARM/arm-shift-encoding.s
Normal file
@ -0,0 +1,76 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7 -show-encoding < %s | FileCheck %s
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ldr r0, [r0, r0]
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ldr r0, [r0, r0, lsr #32]
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ldr r0, [r0, r0, lsr #16]
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ldr r0, [r0, r0, lsl #0]
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ldr r0, [r0, r0, lsl #16]
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ldr r0, [r0, r0, asr #32]
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ldr r0, [r0, r0, asr #16]
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ldr r0, [r0, r0, rrx]
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ldr r0, [r0, r0, ror #16]
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@ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
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@ CHECK: ldr r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x90,0xe7]
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pld [r0, r0]
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pld [r0, r0, lsr #32]
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pld [r0, r0, lsr #16]
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pld [r0, r0, lsl #0]
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pld [r0, r0, lsl #16]
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pld [r0, r0, asr #32]
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pld [r0, r0, asr #16]
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pld [r0, r0, rrx]
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pld [r0, r0, ror #16]
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@ CHECK: [r0, r0] @ encoding: [0x00,0xf0,0xd0,0xf7]
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@ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
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@ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
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@ CHECK: [r0, r0] @ encoding: [0x00,0xf0,0xd0,0xf7]
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@ CHECK: [r0, r0, lsl #16] @ encoding: [0x00,0xf8,0xd0,0xf7]
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@ CHECK: [r0, r0, asr #32] @ encoding: [0x40,0xf0,0xd0,0xf7]
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@ CHECK: [r0, r0, asr #16] @ encoding: [0x40,0xf8,0xd0,0xf7]
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@ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
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@ CHECK: [r0, r0, ror #16] @ encoding: [0x60,0xf8,0xd0,0xf7]
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str r0, [r0, r0]
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str r0, [r0, r0, lsr #32]
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str r0, [r0, r0, lsr #16]
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str r0, [r0, r0, lsl #0]
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str r0, [r0, r0, lsl #16]
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str r0, [r0, r0, asr #32]
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str r0, [r0, r0, asr #16]
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str r0, [r0, r0, rrx]
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str r0, [r0, r0, ror #16]
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@ CHECK: str r0, [r0, r0] @ encoding: [0x00,0x00,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x80,0xe7]
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@ CHECK: str r0, [r0, r0] @ encoding: [0x00,0x00,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
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@ CHECK: str r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x80,0xe7]
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@ Uses printAddrMode2OffsetOperand(), used by LDRBT_POST_IMM LDRBT_POST_REG
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@ LDRB_POST_IMM LDRB_POST_REG LDRT_POST_IMM LDRT_POST_REG LDR_POST_IMM
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@ LDR_POST_REG STRBT_POST_IMM STRBT_POST_REG STRB_POST_IMM STRB_POST_REG
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@ STRT_POST_IMM STRT_POST_REG STR_POST_IMM STR_POST_REG
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ldr r0, [r1], r2, rrx
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ldr r3, [r4], r5, ror #0
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str r6, [r7], r8, lsl #0
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str r9, [r10], r11
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@ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
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@ CHECK: ldr r3, [r4], r5 @ encoding: [0x05,0x30,0x94,0xe6]
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@ CHECK: str r6, [r7], r8 @ encoding: [0x08,0x60,0x87,0xe6]
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@ CHECK: str r9, [r10], r11 @ encoding: [0x0b,0x90,0x8a,0xe6]
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@ -47,7 +47,47 @@
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, ror #32
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@ Out of range shift immediate values for load/store.
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str r1, [r2, r3, lsl #invalid]
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ldr r4, [r5], r6, lsl #-1
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pld r4, [r5, r6, lsl #32]
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str r4, [r5], r6, lsr #-1
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ldr r4, [r5, r6, lsr #33]
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pld r4, [r5, r6, asr #-1]
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str r4, [r5, r6, asr #33]
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ldr r4, [r5, r6, ror #-1]
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pld r4, [r5, r6, ror #32]
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pld r4, [r5, r6, rrx #0]
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@ CHECK-ERRORS: error: shift amount must be an immediate
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@ CHECK-ERRORS: str r1, [r2, r3, lsl #invalid]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5], r6, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, lsl #32]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5], r6, lsr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, lsr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, asr #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5, r6, asr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, ror #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, ror #32]
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@ CHECK-ERRORS: error: ']' expected
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@ CHECK-ERRORS: pld r4, [r5, r6, rrx #0]
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@ Out of range 16-bit immediate on BKPT
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bkpt #65536
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