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remove variable names from comments; NFC
I didn't bother to fix the self-referential definitions and grammar because my eyes started to bleed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
parent
69e4dd1b12
commit
93e763c5cb
@ -31,7 +31,7 @@ class GlobalValue;
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class StringRef;
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class TargetMachine;
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/// PICStyles - The X86 backend supports a number of different styles of PIC.
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/// The X86 backend supports a number of different styles of PIC.
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///
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namespace PICStyles {
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enum Style {
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@ -58,105 +58,101 @@ protected:
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Others, IntelAtom, IntelSLM
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};
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/// X86ProcFamily - X86 processor family: Intel Atom, and others
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/// X86 processor family: Intel Atom, and others
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X86ProcFamilyEnum X86ProcFamily;
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/// PICStyle - Which PIC style to use
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///
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/// Which PIC style to use
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PICStyles::Style PICStyle;
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/// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
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/// none supported.
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/// MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
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X86SSEEnum X86SSELevel;
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/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
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///
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/// 3DNow, 3DNow Athlon, or none supported.
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X863DNowEnum X863DNowLevel;
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/// HasCMov - True if this processor has conditional move instructions
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/// True if this processor has conditional move instructions
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/// (generally pentium pro+).
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bool HasCMov;
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/// HasX86_64 - True if the processor supports X86-64 instructions.
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///
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/// True if the processor supports X86-64 instructions.
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bool HasX86_64;
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/// HasPOPCNT - True if the processor supports POPCNT.
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/// True if the processor supports POPCNT.
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bool HasPOPCNT;
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/// HasSSE4A - True if the processor supports SSE4A instructions.
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/// True if the processor supports SSE4A instructions.
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bool HasSSE4A;
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/// HasAES - Target has AES instructions
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/// Target has AES instructions
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bool HasAES;
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/// HasPCLMUL - Target has carry-less multiplication
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/// Target has carry-less multiplication
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bool HasPCLMUL;
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/// HasFMA - Target has 3-operand fused multiply-add
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/// Target has 3-operand fused multiply-add
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bool HasFMA;
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/// HasFMA4 - Target has 4-operand fused multiply-add
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/// Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// HasXOP - Target has XOP instructions
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/// Target has XOP instructions
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bool HasXOP;
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/// HasTBM - Target has TBM instructions.
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/// Target has TBM instructions.
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bool HasTBM;
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/// HasMOVBE - True if the processor has the MOVBE instruction.
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/// True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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/// HasRDRAND - True if the processor has the RDRAND instruction.
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/// True if the processor has the RDRAND instruction.
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bool HasRDRAND;
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/// HasF16C - Processor has 16-bit floating point conversion instructions.
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/// Processor has 16-bit floating point conversion instructions.
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bool HasF16C;
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/// HasFSGSBase - Processor has FS/GS base insturctions.
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/// Processor has FS/GS base insturctions.
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bool HasFSGSBase;
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/// HasLZCNT - Processor has LZCNT instruction.
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/// Processor has LZCNT instruction.
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bool HasLZCNT;
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/// HasBMI - Processor has BMI1 instructions.
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/// Processor has BMI1 instructions.
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bool HasBMI;
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/// HasBMI2 - Processor has BMI2 instructions.
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/// Processor has BMI2 instructions.
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bool HasBMI2;
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/// HasRTM - Processor has RTM instructions.
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/// Processor has RTM instructions.
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bool HasRTM;
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/// HasHLE - Processor has HLE.
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/// Processor has HLE.
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bool HasHLE;
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/// HasADX - Processor has ADX instructions.
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/// Processor has ADX instructions.
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bool HasADX;
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/// HasSHA - Processor has SHA instructions.
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/// Processor has SHA instructions.
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bool HasSHA;
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/// HasSGX - Processor has SGX instructions.
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/// Processor has SGX instructions.
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bool HasSGX;
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/// HasPRFCHW - Processor has PRFCHW instructions.
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/// Processor has PRFCHW instructions.
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bool HasPRFCHW;
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/// HasRDSEED - Processor has RDSEED instructions.
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/// Processor has RDSEED instructions.
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bool HasRDSEED;
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/// HasSMAP - Processor has SMAP instructions.
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/// Processor has SMAP instructions.
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bool HasSMAP;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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/// True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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/// IsSHLDSlow - True if SHLD instructions are slow.
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/// True if SHLD instructions are slow.
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bool IsSHLDSlow;
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/// IsUAMemFast - True if unaligned memory access is fast.
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/// True if unaligned memory access is fast.
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bool IsUAMemFast;
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/// True if unaligned 32-byte memory accesses are slow.
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@ -166,37 +162,38 @@ protected:
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/// This may require setting a configuration bit in the processor.
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bool HasSSEUnalignedMem;
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/// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
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/// True if this processor has the CMPXCHG16B instruction;
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/// this is true for most x86-64 chips, but not the first AMD chips.
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bool HasCmpxchg16b;
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/// UseLeaForSP - True if the LEA instruction should be used for adjusting
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/// True if the LEA instruction should be used for adjusting
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/// the stack pointer. This is an optimization for Intel Atom processors.
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bool UseLeaForSP;
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/// HasSlowDivide32 - True if 8-bit divisions are significantly faster than
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/// True if 8-bit divisions are significantly faster than
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/// 32-bit divisions and should be used when possible.
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bool HasSlowDivide32;
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/// HasSlowDivide64 - True if 16-bit divides are significantly faster than
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/// True if 16-bit divides are significantly faster than
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/// 64-bit divisions and should be used when possible.
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bool HasSlowDivide64;
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/// PadShortFunctions - True if the short functions should be padded to prevent
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/// True if the short functions should be padded to prevent
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/// a stall when returning too early.
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bool PadShortFunctions;
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/// CallRegIndirect - True if the Calls with memory reference should be converted
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/// True if the Calls with memory reference should be converted
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/// to a register-based indirect call.
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bool CallRegIndirect;
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/// LEAUsesAG - True if the LEA instruction inputs have to be ready at
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/// address generation (AG) time.
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/// True if the LEA instruction inputs have to be ready at address generation
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/// (AG) time.
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bool LEAUsesAG;
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/// SlowLEA - True if the LEA instruction with certain arguments is slow
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/// True if the LEA instruction with certain arguments is slow
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bool SlowLEA;
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/// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
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/// True if INC and DEC instructions are slow when writing to flags
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bool SlowIncDec;
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/// Use the RSQRT* instructions to optimize square root calculations.
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@ -227,7 +224,7 @@ protected:
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/// Processor has AVX-512 Vector Length eXtenstions
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bool HasVLX;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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@ -235,7 +232,7 @@ protected:
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///
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unsigned MaxInlineSizeThreshold;
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/// TargetTriple - What processor and OS we're targeting.
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/// What processor and OS we're targeting.
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Triple TargetTriple;
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/// Instruction itineraries for scheduling
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@ -243,16 +240,16 @@ protected:
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private:
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/// StackAlignOverride - Override the stack alignment.
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/// Override the stack alignment.
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unsigned StackAlignOverride;
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/// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
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/// True if compiling for 64-bit, false for 16-bit or 32-bit.
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bool In64BitMode;
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/// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
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/// True if compiling for 32-bit, false for 16-bit or 64-bit.
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bool In32BitMode;
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/// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
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/// True if compiling for 16-bit, false for 32-bit or 64-bit.
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bool In16BitMode;
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X86SelectionDAGInfo TSInfo;
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@ -284,12 +281,12 @@ public:
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return &getInstrInfo()->getRegisterInfo();
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}
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return stackAlignment; }
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
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@ -298,7 +295,7 @@ public:
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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private:
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/// \brief Initialize the full set of dependencies so we can use an initializer
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/// Initialize the full set of dependencies so we can use an initializer
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/// list for X86Subtarget.
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X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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void initializeEnvironment();
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@ -473,13 +470,11 @@ public:
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unsigned char ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM)const;
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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/// Classify a blockaddress reference for the current subtarget according to
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/// how we should reference it in a non-pcrel context.
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unsigned char ClassifyBlockAddressReference() const;
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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/// Return true if the subtarget allows calls to immediate address.
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bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
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/// This function returns the name of a function which has an interface
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@ -498,8 +493,7 @@ public:
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bool enableEarlyIfConversion() const override;
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/// getInstrItins = Return the instruction itineraries based on the
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/// subtarget selection.
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/// Return the instruction itineraries based on the subtarget selection.
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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