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Remove trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243838 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -410,7 +410,7 @@ namespace {
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void getStoreMergeAndAliasCandidates(
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void getStoreMergeAndAliasCandidates(
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StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
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StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
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SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);
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SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);
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/// Merge consecutive store operations into a wide store.
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/// Merge consecutive store operations into a wide store.
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/// This optimization uses wide integers or vectors when possible.
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/// This optimization uses wide integers or vectors when possible.
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/// \return True if some memory operations were changed.
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/// \return True if some memory operations were changed.
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@ -5563,7 +5563,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
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SDLoc(N));
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SDLoc(N));
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}
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}
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/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
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/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
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/// a build_vector of constants.
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/// a build_vector of constants.
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/// This function is called by the DAGCombiner when visiting sext/zext/aext
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/// This function is called by the DAGCombiner when visiting sext/zext/aext
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/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
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/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
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@ -8238,13 +8238,13 @@ SDValue DAGCombiner::visitFMA(SDNode *N) {
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SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
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SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
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if (!DAG.getTarget().Options.UnsafeFPMath)
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if (!DAG.getTarget().Options.UnsafeFPMath)
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return SDValue();
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return SDValue();
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// Skip if current node is a reciprocal.
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// Skip if current node is a reciprocal.
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SDValue N0 = N->getOperand(0);
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SDValue N0 = N->getOperand(0);
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ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
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if (N0CFP && N0CFP->isExactlyValue(1.0))
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if (N0CFP && N0CFP->isExactlyValue(1.0))
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return SDValue();
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return SDValue();
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// Exit early if the target does not want this transform or if there can't
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// Exit early if the target does not want this transform or if there can't
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// possibly be enough uses of the divisor to make the transform worthwhile.
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// possibly be enough uses of the divisor to make the transform worthwhile.
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SDValue N1 = N->getOperand(1);
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SDValue N1 = N->getOperand(1);
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@ -8416,7 +8416,7 @@ SDValue DAGCombiner::visitFSQRT(SDNode *N) {
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SDValue RV = BuildRsqrtEstimate(N->getOperand(0));
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SDValue RV = BuildRsqrtEstimate(N->getOperand(0));
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if (!RV)
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if (!RV)
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return SDValue();
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return SDValue();
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EVT VT = RV.getValueType();
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EVT VT = RV.getValueType();
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SDLoc DL(N);
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SDLoc DL(N);
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RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV);
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RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV);
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@ -10851,12 +10851,12 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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// We need to make sure that these nodes do not interfere with
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// We need to make sure that these nodes do not interfere with
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// any of the store nodes.
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// any of the store nodes.
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SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
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SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
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// Save the StoreSDNodes that we find in the chain.
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// Save the StoreSDNodes that we find in the chain.
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SmallVector<MemOpLink, 8> StoreNodes;
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SmallVector<MemOpLink, 8> StoreNodes;
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getStoreMergeAndAliasCandidates(St, StoreNodes, AliasLoadNodes);
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getStoreMergeAndAliasCandidates(St, StoreNodes, AliasLoadNodes);
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// Check if there is anything to merge.
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// Check if there is anything to merge.
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if (StoreNodes.size() < 2)
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if (StoreNodes.size() < 2)
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return false;
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return false;
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