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Improve lowering of sext to i128 on SPU.

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The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-10-18 09:34:19 +00:00
parent 4cf34c6c04
commit 940e7965f1
2 changed files with 10 additions and 2 deletions
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9
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -2642,11 +2642,16 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
DAG.getConstant(31, MVT::i32));
// reinterpret as a i128 (SHUFB requires it). This gets lowered away.
SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
dl, Op0VT, Op0,
DAG.getTargetConstant(
SPU::GPRCRegClass.getID(),
MVT::i32)), 0);
// Shuffle bytes - Copy the sign bits into the upper 64 bits
// and the input value into the lower 64 bits.
SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
extended, sraVal, shufMask);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
}

3
test/CodeGen/CellSPU/sext128.ll
View File

@ -12,6 +12,7 @@ entry:
; CHECK: long 269488144
; CHECK: long 66051
; CHECK: long 67438087
; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb
@ -25,6 +26,7 @@ entry:
; CHECK: long 269488144
; CHECK: long 269488144
; CHECK: long 66051
; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb
@ -39,6 +41,7 @@ entry:
; CHECK: long 269488144
; CHECK: long 269488144
; CHECK: long 66051
; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb