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Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
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a0b3909d43
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@ -221,7 +221,7 @@ public:
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}
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}
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/// copyRegToReg - Add a copy between a pair of registers
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/// copyRegToReg - Add a copy between a pair of registers
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -250,9 +250,6 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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// Unhandled type. Halt "fast" selection and bail.
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return I;
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return I;
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if (!TLI.isConvertLegal(SrcVT, DstVT))
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// Illegal conversion. Halt "fast" selection and bail.
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return I;
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// Otherwise, insert a register-to-register copy.
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// Otherwise, insert a register-to-register copy.
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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@ -264,9 +261,12 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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// Unhandled operand. Halt "fast" selection and bail.
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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return false;
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TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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ValueMap[I] = ResultReg;
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Op0, DstClass, SrcClass);
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if (!InsertedCopy)
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return I;
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ValueMap[I] = ResultReg;
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break;
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break;
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} else
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} else
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// TODO: Casting a non-integral constant?
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// TODO: Casting a non-integral constant?
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@ -459,14 +459,14 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T
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return 2;
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return 2;
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}
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}
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void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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// Not yet supported!
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abort();
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return false;
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}
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}
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if (DestRC == ARM::GPRRegisterClass) {
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if (DestRC == ARM::GPRRegisterClass) {
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@ -484,7 +484,9 @@ void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
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AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
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.addReg(SrcReg));
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.addReg(SrcReg));
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else
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else
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abort();
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return false;
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return true;
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}
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}
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static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
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static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
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@ -163,7 +163,7 @@ public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -133,15 +133,15 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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return 2;
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return 2;
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}
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}
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void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
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//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
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if (DestRC != SrcRC) {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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// Not yet supported!
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abort();
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return false;
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}
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}
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if (DestRC == Alpha::GPRCRegisterClass) {
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if (DestRC == Alpha::GPRCRegisterClass) {
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@ -151,9 +151,11 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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} else if (DestRC == Alpha::F8RCRegisterClass) {
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} else if (DestRC == Alpha::F8RCRegisterClass) {
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BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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} else {
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cerr << "Attempt to copy register that is not GPR or FPR";
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// Attempt to copy register that is not GPR or FPR
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abort();
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return false;
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}
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}
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return true;
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}
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}
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void
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void
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@ -42,7 +42,7 @@ public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -180,7 +180,7 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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return 0;
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return 0;
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}
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}
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void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -218,9 +218,11 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
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BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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.addReg(SrcReg);
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} else {
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} else {
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cerr << "Attempt to copy unknown/unsupported register class!\n";
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// Attempt to copy unknown/unsupported register class!
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abort();
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return false;
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}
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}
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return true;
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}
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}
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void
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void
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@ -46,7 +46,7 @@ namespace llvm {
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unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -57,14 +57,14 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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return 1;
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return 1;
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}
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}
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void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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// Not yet supported!
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abort();
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return false;
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}
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}
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if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
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if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
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@ -73,6 +73,8 @@ void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
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.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
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else // otherwise, MOV works (for both gen. regs and FP regs)
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else // otherwise, MOV works (for both gen. regs and FP regs)
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BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
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BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
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return true;
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}
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}
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void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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@ -40,7 +40,7 @@ public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -118,7 +118,7 @@ insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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BuildMI(MBB, MI, get(Mips::NOP));
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BuildMI(MBB, MI, get(Mips::NOP));
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}
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}
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void MipsInstrInfo::
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bool MipsInstrInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -141,10 +141,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
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else if ((SrcRC == Mips::CCRRegisterClass) &&
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else if ((SrcRC == Mips::CCRRegisterClass) &&
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(SrcReg == Mips::FCR31))
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(SrcReg == Mips::FCR31))
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return; // This register is used implicitly, no copy needed.
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return true; // This register is used implicitly, no copy needed.
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else if ((DestRC == Mips::CCRRegisterClass) &&
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else if ((DestRC == Mips::CCRRegisterClass) &&
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(DestReg == Mips::FCR31))
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(DestReg == Mips::FCR31))
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return; // This register is used implicitly, no copy needed.
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return true; // This register is used implicitly, no copy needed.
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else if ((DestRC == Mips::HILORegisterClass) &&
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else if ((DestRC == Mips::HILORegisterClass) &&
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(SrcRC == Mips::CPURegsRegisterClass)) {
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(SrcRC == Mips::CPURegsRegisterClass)) {
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unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
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unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
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@ -154,9 +154,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
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unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
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BuildMI(MBB, I, get(Opc), DestReg);
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BuildMI(MBB, I, get(Opc), DestReg);
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} else
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} else
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assert (0 && "DestRC != SrcRC, Can't copy this register");
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// DestRC != SrcRC, Can't copy this register
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return false;
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return;
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return true;
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}
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}
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if (DestRC == Mips::CPURegsRegisterClass)
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if (DestRC == Mips::CPURegsRegisterClass)
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@ -169,7 +170,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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else if (DestRC == Mips::AFGR64RegisterClass)
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else if (DestRC == Mips::AFGR64RegisterClass)
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BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
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else
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else
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assert (0 && "Can't copy this register");
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// Can't copy this register
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return false;
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return true;
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}
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}
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void MipsInstrInfo::
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void MipsInstrInfo::
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@ -169,7 +169,7 @@ public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -315,14 +315,14 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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return 2;
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return 2;
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}
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}
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void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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// Not yet supported!
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abort();
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return false;
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}
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}
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if (DestRC == PPC::GPRCRegisterClass) {
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if (DestRC == PPC::GPRCRegisterClass) {
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@ -340,9 +340,11 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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} else if (DestRC == PPC::CRBITRCRegisterClass) {
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} else if (DestRC == PPC::CRBITRCRegisterClass) {
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BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
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BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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} else {
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cerr << "Attempt to copy register that is not GPR or FPR";
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// Attempt to copy register that is not GPR or FPR
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abort();
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return false;
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}
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}
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return true;
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}
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}
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bool
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bool
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@ -112,7 +112,7 @@ public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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@ -109,14 +109,14 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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return 1;
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return 1;
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}
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}
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void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
|
if (DestRC != SrcRC) {
|
||||||
cerr << "Not yet supported!";
|
// Not yet supported!
|
||||||
abort();
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (DestRC == SP::IntRegsRegisterClass)
|
if (DestRC == SP::IntRegsRegisterClass)
|
||||||
@ -127,7 +127,10 @@ void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
|
BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
|
||||||
.addReg(SrcReg);
|
.addReg(SrcReg);
|
||||||
else
|
else
|
||||||
assert (0 && "Can't copy this register");
|
// Can't copy this register
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void SparcInstrInfo::
|
void SparcInstrInfo::
|
||||||
|
@ -68,7 +68,7 @@ public:
|
|||||||
MachineBasicBlock *FBB,
|
MachineBasicBlock *FBB,
|
||||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||||
|
|
||||||
virtual void copyRegToReg(MachineBasicBlock &MBB,
|
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
|
@ -1592,7 +1592,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|||||||
return 2;
|
return 2;
|
||||||
}
|
}
|
||||||
|
|
||||||
void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
@ -1626,11 +1626,10 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
} else if (DestRC == &X86::VR64RegClass) {
|
} else if (DestRC == &X86::VR64RegClass) {
|
||||||
Opc = X86::MMX_MOVQ64rr;
|
Opc = X86::MMX_MOVQ64rr;
|
||||||
} else {
|
} else {
|
||||||
assert(0 && "Unknown regclass");
|
return false;
|
||||||
abort();
|
|
||||||
}
|
}
|
||||||
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
|
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Moving EFLAGS to / from another register requires a push and a pop.
|
// Moving EFLAGS to / from another register requires a push and a pop.
|
||||||
@ -1639,30 +1638,31 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
if (DestRC == &X86::GR64RegClass) {
|
if (DestRC == &X86::GR64RegClass) {
|
||||||
BuildMI(MBB, MI, get(X86::PUSHFQ));
|
BuildMI(MBB, MI, get(X86::PUSHFQ));
|
||||||
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
|
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
|
||||||
return;
|
return true;
|
||||||
} else if (DestRC == &X86::GR32RegClass) {
|
} else if (DestRC == &X86::GR32RegClass) {
|
||||||
BuildMI(MBB, MI, get(X86::PUSHFD));
|
BuildMI(MBB, MI, get(X86::PUSHFD));
|
||||||
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
|
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
} else if (DestRC == &X86::CCRRegClass) {
|
} else if (DestRC == &X86::CCRRegClass) {
|
||||||
assert(DestReg == X86::EFLAGS);
|
assert(DestReg == X86::EFLAGS);
|
||||||
if (SrcRC == &X86::GR64RegClass) {
|
if (SrcRC == &X86::GR64RegClass) {
|
||||||
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
|
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
|
||||||
BuildMI(MBB, MI, get(X86::POPFQ));
|
BuildMI(MBB, MI, get(X86::POPFQ));
|
||||||
return;
|
return true;
|
||||||
} else if (SrcRC == &X86::GR32RegClass) {
|
} else if (SrcRC == &X86::GR32RegClass) {
|
||||||
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
|
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
|
||||||
BuildMI(MBB, MI, get(X86::POPFD));
|
BuildMI(MBB, MI, get(X86::POPFD));
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Moving from ST(0) turns into FpGET_ST0_32 etc.
|
// Moving from ST(0) turns into FpGET_ST0_32 etc.
|
||||||
if (SrcRC == &X86::RSTRegClass) {
|
if (SrcRC == &X86::RSTRegClass) {
|
||||||
// Copying from ST(0)/ST(1).
|
// Copying from ST(0)/ST(1).
|
||||||
assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
|
if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
|
||||||
"Can only copy from ST(0)/ST(1) right now");
|
// Can only copy from ST(0)/ST(1) right now
|
||||||
|
return false;
|
||||||
bool isST0 = SrcReg == X86::ST0;
|
bool isST0 = SrcReg == X86::ST0;
|
||||||
unsigned Opc;
|
unsigned Opc;
|
||||||
if (DestRC == &X86::RFP32RegClass)
|
if (DestRC == &X86::RFP32RegClass)
|
||||||
@ -1674,13 +1674,15 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
|
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
|
||||||
}
|
}
|
||||||
BuildMI(MBB, MI, get(Opc), DestReg);
|
BuildMI(MBB, MI, get(Opc), DestReg);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Moving to ST(0) turns into FpSET_ST0_32 etc.
|
// Moving to ST(0) turns into FpSET_ST0_32 etc.
|
||||||
if (DestRC == &X86::RSTRegClass) {
|
if (DestRC == &X86::RSTRegClass) {
|
||||||
// Copying to ST(0). FIXME: handle ST(1) also
|
// Copying to ST(0). FIXME: handle ST(1) also
|
||||||
assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
|
if (DestReg != X86::ST0)
|
||||||
|
// Can only copy to TOS right now
|
||||||
|
return false;
|
||||||
unsigned Opc;
|
unsigned Opc;
|
||||||
if (SrcRC == &X86::RFP32RegClass)
|
if (SrcRC == &X86::RFP32RegClass)
|
||||||
Opc = X86::FpSET_ST0_32;
|
Opc = X86::FpSET_ST0_32;
|
||||||
@ -1691,11 +1693,11 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
Opc = X86::FpSET_ST0_80;
|
Opc = X86::FpSET_ST0_80;
|
||||||
}
|
}
|
||||||
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
|
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
assert(0 && "Not yet supported!");
|
// Not yet supported!
|
||||||
abort();
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
|
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
|
||||||
|
@ -311,7 +311,7 @@ public:
|
|||||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||||
MachineBasicBlock *FBB,
|
MachineBasicBlock *FBB,
|
||||||
const SmallVectorImpl<MachineOperand> &Cond) const;
|
const SmallVectorImpl<MachineOperand> &Cond) const;
|
||||||
virtual void copyRegToReg(MachineBasicBlock &MBB,
|
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
|
Loading…
Reference in New Issue
Block a user