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add an option to turn on LSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26080 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -493,6 +493,7 @@ def UMULrr : F3_1<2, 0b001010,
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def UMULri : F3_2<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umul $b, $c, $dst", []>;
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def SMULrr : F3_1<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smul $b, $c, $dst",
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@ -502,6 +503,61 @@ def SMULri : F3_2<2, 0b001011,
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"smul $b, $c, $dst",
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[(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
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/*
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//===-------------------------
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// Sparc Example
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defm intinst<id OPC1, id OPC2, bits Opc, string asmstr, SDNode code> {
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def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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[(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>;
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def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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[(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>;
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}
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defm intinst_np<id OPC1, id OPC2, bits Opc, string asmstr> {
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def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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[]>;
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def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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[]>;
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}
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def intinstnp< ADDXrr, ADDXri, 0b001000, "addx $b, $c, $dst">;
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def intinst < SUBrr, SUBri, 0b000100, "sub $b, $c, $dst", sub>;
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def intinstnp< SUBXrr, SUBXri, 0b001100, "subx $b, $c, $dst">;
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def intinst <SUBCCrr, SUBCCri, 0b010100, "subcc $b, $c, $dst", SPcmpicc>;
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def intinst < SMULrr, SMULri, 0b001011, "smul $b, $c, $dst", mul>;
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//===-------------------------
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// X86 Example
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defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> {
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def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
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asmstr+" {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB;
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def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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asmstr+" {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (X86cmov R32:$src1,
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(loadi32 addr:$src2), cond))]>, TB;
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}
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def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>;
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def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>;
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//===-------------------------
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// PPC Example
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def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr,
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SDNode code> {
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def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB),
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asmstr+" $frD, $frB", FPGeneral,
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[(set F4RC:$frD, (code F4RC:$frB))]>;
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def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB),
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asmstr+" $frD, $frB", FPGeneral,
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[(set F8RC:$frD, (code F8RC:$frB))]>;
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}
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def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>;
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def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>;
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def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>;
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*/
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr : F3_1<2, 0b001110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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@ -27,6 +27,8 @@ using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcTargetMachine> X("sparc", " SPARC");
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cl::opt<bool> EnableLSR("enable-sparc-lsr", cl::Hidden);
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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@ -65,6 +67,9 @@ bool SparcTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
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bool Fast) {
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if (FileType != TargetMachine::AssemblyFile) return true;
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// Run loop strength reduction before anything else.
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if (EnableLSR && !Fast) PM.add(createLoopStrengthReducePass());
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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