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synced 2024-12-13 20:32:21 +00:00
hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and use it in DAGISelMatcherGen.cpp instead of using an incorrect predicate that happened to get lucky on our current targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -779,15 +779,9 @@ static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
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// FIXME: Should allow access to all the results here.
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unsigned NumDefsToAdd = InstInfo.NumDefs ? 1 : 0;
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if (!InstInfo.ImplicitDefs.empty()) {
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// Add on one implicit def if it has a resolvable type.
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Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
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assert(FirstImplicitDef->isSubClassOf("Register"));
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const std::vector<MVT::SimpleValueType> &RegVTs =
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CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
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if (RegVTs.size() == 1)
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return NumDefsToAdd+1;
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}
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// Add on one implicit def if it has a resolvable type.
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if (InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo()) !=MVT::Other)
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++NumDefsToAdd;
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return NumDefsToAdd;
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}
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@ -1279,12 +1273,13 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
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if (!InstInfo.ImplicitDefs.empty()) {
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unsigned ResNo = NumResultsToAdd;
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Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
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assert(FirstImplicitDef->isSubClassOf("Register"));
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const std::vector<MVT::SimpleValueType> &RegVTs =
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CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
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if (RegVTs.size() == 1) // FIXME: Generalize.
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MadeChange |= UpdateNodeType(ResNo, EEVT::TypeSet(RegVTs), TP);
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// FIXME: Generalize to multiple possible types and multiple possible
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// ImplicitDefs.
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MVT::SimpleValueType VT =
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InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo());
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if (VT != MVT::Other)
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MadeChange |= UpdateNodeType(ResNo, VT, TP);
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}
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// If this is an INSERT_SUBREG, constrain the source and destination VTs to
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@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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@ -294,3 +295,22 @@ CodeGenInstruction::ParseOperandName(const std::string &Op,
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// Otherwise, didn't find it!
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throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
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}
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/// HasOneImplicitDefWithKnownVT - If the instruction has at least one
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/// implicit def and it has a known VT, return the VT, otherwise return
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/// MVT::Other.
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MVT::SimpleValueType CodeGenInstruction::
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HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
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if (ImplicitDefs.empty()) return MVT::Other;
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// Check to see if the first implicit def has a resolvable type.
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Record *FirstImplicitDef = ImplicitDefs[0];
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assert(FirstImplicitDef->isSubClassOf("Register"));
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const std::vector<MVT::SimpleValueType> &RegVTs =
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TargetInfo.getRegisterVTs(FirstImplicitDef);
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if (RegVTs.size() == 1)
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return RegVTs[0];
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return MVT::Other;
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}
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@ -22,6 +22,7 @@
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namespace llvm {
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class Record;
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class DagInit;
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class CodeGenTarget;
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class CodeGenInstruction {
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public:
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@ -183,6 +184,12 @@ namespace llvm {
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/// non-empty name. If the instruction does not have an operand with the
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/// specified name, throw an exception.
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unsigned getOperandNamed(const std::string &Name) const;
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/// HasOneImplicitDefWithKnownVT - If the instruction has at least one
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/// implicit def and it has a known VT, return the VT, otherwise return
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/// MVT::Other.
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MVT::SimpleValueType
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HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
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};
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}
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@ -733,8 +733,7 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
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// If the root came from an implicit def in the instruction handling stuff,
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// don't re-add it.
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Record *HandledReg = 0;
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if (N->getNumTypes() != 0 &&
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!II.ImplicitDefs.empty())
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if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
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HandledReg = II.ImplicitDefs[0];
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for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
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