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ARM vmrs system registers mvfr0 and mvfr1 handling.
rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1212,6 +1212,10 @@ let Uses = [FPSCR] in {
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"vmrs", "\t$Rt, fpexc", []>;
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def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, fpsid", []>;
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def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr0", []>;
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def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
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"vmrs", "\t$Rt, mvfr1", []>;
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}
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//===----------------------------------------------------------------------===//
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@ -166,6 +166,8 @@ def ITSTATE : ARMReg<4, "itstate">;
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// Special Registers - only available in privileged mode.
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def FPSID : ARMReg<0, "fpsid">;
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def MVFR1 : ARMReg<6, "mvfr1">;
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def MVFR0 : ARMReg<7, "mvfr0">;
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def FPEXC : ARMReg<8, "fpexc">;
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// Register classes.
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@ -120,12 +120,21 @@
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@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
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vnmls.f32 s1, s2, s0
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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vmrs APSR_nzcv, fpscr
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vmrs apsr_nzcv, fpscr
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fmstat
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vmrs r2, fpsid
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vmrs r3, FPSID
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vmrs r4, mvfr0
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vmrs r5, MVFR1
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
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@ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
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@ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
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@ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
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@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
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vnegne.f64 d16, d16
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