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R600/SI: Improve BFM support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233077 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1406,6 +1406,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
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case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
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case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
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case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
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case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
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case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
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case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
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@ -308,7 +308,8 @@ defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64",
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>;
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} // End Defs = [SCC]
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defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", []>;
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defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32",
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[(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
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defm S_BFM_B64 : SOP2_64 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
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defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
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[(set i32:$dst, (mul i32:$src0, i32:$src1))]
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@ -1613,8 +1614,8 @@ defm V_MAC_LEGACY_F32 : VOP2_VI3_Inst <vop23<0x6, 0x28e>, "v_mac_legacy_f32",
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>;
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} // End isCommutable = 1
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defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", VOP_I32_I32_I32,
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AMDGPUbfm
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defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
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VOP_I32_I32_I32
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>;
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defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
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VOP_I32_I32_I32
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@ -3323,6 +3324,21 @@ def : Pat <
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(V_CNDMASK_B32_e64 $src0, $src1, $src2)
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>;
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multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
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def : Pat <
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(vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
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(BFM $a, $b)
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>;
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def : Pat <
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(vt (add (vt (shl 1, vt:$a)), -1)),
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(BFM $a, (MOV 0))
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>;
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}
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defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
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// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
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//===----------------------------------------------------------------------===//
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// Fract Patterns
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//===----------------------------------------------------------------------===//
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@ -5,7 +5,7 @@
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declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone
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; FUNC-LABEL: {{^}}bfm_arg_arg:
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; SI: v_bfm
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; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; EG: BFM_INT
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define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone
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@ -14,7 +14,7 @@ define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind
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}
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; FUNC-LABEL: {{^}}bfm_arg_imm:
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; SI: v_bfm
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; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x7b
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; EG: BFM_INT
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define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind {
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%bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone
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@ -23,7 +23,7 @@ define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind {
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}
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; FUNC-LABEL: {{^}}bfm_imm_arg:
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; SI: v_bfm
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; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, {{s[0-9]+}}
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; EG: BFM_INT
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define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind {
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%bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone
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@ -32,10 +32,29 @@ define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind {
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}
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; FUNC-LABEL: {{^}}bfm_imm_imm:
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; SI: v_bfm
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; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, 0x1c8
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; EG: BFM_INT
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define void @bfm_imm_imm(i32 addrspace(1)* %out) nounwind {
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%bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone
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store i32 %bfm, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfm_pattern:
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; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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define void @bfm_pattern(i32 addrspace(1)* %out, i32 %x, i32 %y) {
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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%c = shl i32 %b, %y
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store i32 %c, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}bfm_pattern_simple:
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; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0
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define void @bfm_pattern_simple(i32 addrspace(1)* %out, i32 %x) {
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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store i32 %b, i32 addrspace(1)* %out
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ret void
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}
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