diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 9254fcd9174..fa27a7531bd 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -1599,10 +1599,6 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
   default:
     llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
 
-  case ARM::FMSTAT:
-    // No further encoding needed.
-    break;
-
   case ARM::FCONSTD:
   case ARM::FCONSTS: {
     // Encode Dd / Sd.
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index a67e64594a3..c7f3f85eec3 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -927,7 +927,9 @@ def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
   let Inst{15-12} = 0b1111;
   let Inst{11-8}  = 0b1010;
   let Inst{7}     = 0;
+  let Inst{6-5}   = 0b00;
   let Inst{4}     = 1;
+  let Inst{3-0}   = 0b0000;
 }
 
 // FPSCR <-> GPR (for disassembly only)
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index 90f81696bda..84ccb6d005a 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -331,6 +331,8 @@ entry:
   ret float %sub
 }
 
+; FIXME: Check for fmstat instruction.
+
 define i32 @f100() nounwind readnone {
 entry:
 ; CHECK: f100