6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

PPC rotate instructions don't have unmodeled side effcts

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-04-07 15:06:53 +00:00
parent 7ea2e48694
commit 946a811ef1
2 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -495,6 +495,7 @@ def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
def RLDIMI : MDForm_1<30, 3,
(outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
@ -522,11 +523,12 @@ def RLWINM8 : MForm_2<21,
"rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
[]>;
let isSelect = 1, neverHasSideEffects = 1 in
let isSelect = 1 in
def ISEL8 : AForm_4<31, 15,
(outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral,
[]>;
} // neverHasSideEffects = 1
} // End FXU Operations.

5
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1554,8 +1554,9 @@ let Uses = [RM] in {
}
}
let neverHasSideEffects = 1 in {
let PPC970_Unit = 1 in { // FXU Operations.
let isSelect = 1, neverHasSideEffects = 1 in
let isSelect = 1 in
def ISEL : AForm_4<31, 15,
(outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral,
@ -1586,7 +1587,7 @@ def RLWNM : MForm_2<23,
"rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
[]>;
}
} // neverHasSideEffects = 1
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns