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Skip liveness verification when MRI->tracksLiveness() is false.
Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
62cf01e4c5
commit
948a44458c
@ -202,6 +202,7 @@ namespace {
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void report(const char *msg, const MachineInstr *MI);
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void report(const char *msg, const MachineOperand *MO, unsigned MONum);
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void checkLiveness(const MachineOperand *MO, unsigned MONum);
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void markReachable(const MachineBasicBlock *MBB);
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void calcRegsPassed();
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void checkPHIOps(const MachineBasicBlock *MBB);
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@ -656,112 +657,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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const unsigned Reg = MO->getReg();
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if (!Reg)
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return;
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if (MRI->tracksLiveness() && !MI->isDebugValue())
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checkLiveness(MO, MONum);
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// Check Live Variables.
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if (MI->isDebugValue()) {
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// Liveness checks are not valid for debug values.
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} else if (MO->isUse() && !MO->isUndef()) {
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regsLiveInButUnused.erase(Reg);
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bool isKill = false;
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unsigned defIdx;
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if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
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// A two-addr use counts as a kill if use and def are the same.
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unsigned DefReg = MI->getOperand(defIdx).getReg();
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if (Reg == DefReg)
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isKill = true;
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else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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report("Two-address instruction operands must be identical",
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MO, MONum);
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}
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} else
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isKill = MO->isKill();
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if (isKill)
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addRegWithSubRegs(regsKilled, Reg);
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// Check that LiveVars knows this kill.
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if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
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MO->isKill()) {
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LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
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if (std::find(VI.Kills.begin(),
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VI.Kills.end(), MI) == VI.Kills.end())
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report("Kill missing from LiveVariables", MO, MONum);
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}
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// Check LiveInts liveness and kill.
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if (TargetRegisterInfo::isVirtualRegister(Reg) &&
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LiveInts && !LiveInts->isNotInMIMap(MI)) {
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SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
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if (LiveInts->hasInterval(Reg)) {
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const LiveInterval &LI = LiveInts->getInterval(Reg);
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if (!LI.liveAt(UseIdx)) {
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report("No live range at use", MO, MONum);
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*OS << UseIdx << " is not live in " << LI << '\n';
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}
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// Check for extra kill flags.
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// Note that we allow missing kill flags for now.
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if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
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report("Live range continues after kill flag", MO, MONum);
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*OS << "Live range: " << LI << '\n';
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}
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} else {
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report("Virtual register has no Live interval", MO, MONum);
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}
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}
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// Use of a dead register.
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if (!regsLive.count(Reg)) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// Reserved registers may be used even when 'dead'.
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if (!isReserved(Reg))
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report("Using an undefined physical register", MO, MONum);
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} else {
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BBInfo &MInfo = MBBInfoMap[MI->getParent()];
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// We don't know which virtual registers are live in, so only complain
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// if vreg was killed in this MBB. Otherwise keep track of vregs that
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// must be live in. PHI instructions are handled separately.
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if (MInfo.regsKilled.count(Reg))
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report("Using a killed virtual register", MO, MONum);
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else if (!MI->isPHI())
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MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
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}
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}
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} else if (MO->isDef()) {
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// Register defined.
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// TODO: verify that earlyclobber ops are not used.
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if (MO->isDead())
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addRegWithSubRegs(regsDead, Reg);
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else
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addRegWithSubRegs(regsDefined, Reg);
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// Verify SSA form.
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if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
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llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
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report("Multiple virtual register defs in SSA form", MO, MONum);
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// Check LiveInts for a live range, but only for virtual registers.
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if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
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!LiveInts->isNotInMIMap(MI)) {
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SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
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if (LiveInts->hasInterval(Reg)) {
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const LiveInterval &LI = LiveInts->getInterval(Reg);
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if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
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assert(VNI && "NULL valno is not allowed");
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if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
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report("Inconsistent valno->def", MO, MONum);
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*OS << "Valno " << VNI->id << " is not defined at "
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<< DefIdx << " in " << LI << '\n';
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}
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} else {
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report("No live range at def", MO, MONum);
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*OS << DefIdx << " is not live in " << LI << '\n';
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}
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} else {
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report("Virtual register has no Live interval", MO, MONum);
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}
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}
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}
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// Check register classes.
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if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
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@ -853,6 +751,115 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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}
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}
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void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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const MachineInstr *MI = MO->getParent();
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const unsigned Reg = MO->getReg();
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// Both use and def operands can read a register.
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if (MO->readsReg()) {
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regsLiveInButUnused.erase(Reg);
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bool isKill = false;
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unsigned defIdx;
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if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
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// A two-addr use counts as a kill if use and def are the same.
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unsigned DefReg = MI->getOperand(defIdx).getReg();
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if (Reg == DefReg)
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isKill = true;
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else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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report("Two-address instruction operands must be identical", MO, MONum);
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}
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} else
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isKill = MO->isKill();
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if (isKill)
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addRegWithSubRegs(regsKilled, Reg);
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// Check that LiveVars knows this kill.
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if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
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MO->isKill()) {
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LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
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if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
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report("Kill missing from LiveVariables", MO, MONum);
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}
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// Check LiveInts liveness and kill.
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if (TargetRegisterInfo::isVirtualRegister(Reg) &&
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LiveInts && !LiveInts->isNotInMIMap(MI)) {
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SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
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if (LiveInts->hasInterval(Reg)) {
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const LiveInterval &LI = LiveInts->getInterval(Reg);
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if (!LI.liveAt(UseIdx)) {
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report("No live range at use", MO, MONum);
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*OS << UseIdx << " is not live in " << LI << '\n';
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}
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// Check for extra kill flags.
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// Note that we allow missing kill flags for now.
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if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
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report("Live range continues after kill flag", MO, MONum);
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*OS << "Live range: " << LI << '\n';
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}
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} else {
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report("Virtual register has no Live interval", MO, MONum);
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}
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}
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// Use of a dead register.
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if (!regsLive.count(Reg)) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// Reserved registers may be used even when 'dead'.
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if (!isReserved(Reg))
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report("Using an undefined physical register", MO, MONum);
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} else {
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BBInfo &MInfo = MBBInfoMap[MI->getParent()];
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// We don't know which virtual registers are live in, so only complain
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// if vreg was killed in this MBB. Otherwise keep track of vregs that
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// must be live in. PHI instructions are handled separately.
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if (MInfo.regsKilled.count(Reg))
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report("Using a killed virtual register", MO, MONum);
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else if (!MI->isPHI())
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MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
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}
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}
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}
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if (MO->isDef()) {
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// Register defined.
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// TODO: verify that earlyclobber ops are not used.
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if (MO->isDead())
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addRegWithSubRegs(regsDead, Reg);
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else
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addRegWithSubRegs(regsDefined, Reg);
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// Verify SSA form.
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if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
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llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
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report("Multiple virtual register defs in SSA form", MO, MONum);
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// Check LiveInts for a live range, but only for virtual registers.
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if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
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!LiveInts->isNotInMIMap(MI)) {
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SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
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if (LiveInts->hasInterval(Reg)) {
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const LiveInterval &LI = LiveInts->getInterval(Reg);
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if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
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assert(VNI && "NULL valno is not allowed");
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if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
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report("Inconsistent valno->def", MO, MONum);
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*OS << "Valno " << VNI->id << " is not defined at "
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<< DefIdx << " in " << LI << '\n';
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}
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} else {
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report("No live range at def", MO, MONum);
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*OS << DefIdx << " is not live in " << LI << '\n';
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}
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} else {
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report("Virtual register has no Live interval", MO, MONum);
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}
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}
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}
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}
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void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
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BBInfo &MInfo = MBBInfoMap[MI->getParent()];
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set_union(MInfo.regsKilled, regsKilled);
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