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https://github.com/c64scene-ar/llvm-6502.git
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This patch adds support for the vector quadword add/sub instructions introduced
in POWER8: vadduqm vaddeuqm vaddcuq vaddecuq vsubuqm vsubeuqm vsubcuq vsubecuq In addition to adding the instructions themselves, it also adds support for the v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and IntrinsicEmitter.cpp). http://reviews.llvm.org/D9081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238144 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kit Barton
@@ -12,46 +12,46 @@
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; VSX:
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; %a is passed in register 34
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; On LE, ensure %a is swapped before being used (using xxswapd)
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; Similarly, on LE ensure the results are swapped before being returned in
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; register 34
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; The value of 1 is stored in the TOC.
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; On LE, ensure the value of 1 is swapped before being used (using xxswapd).
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; VMX (no VSX):
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; %a is passed in register 2
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; No swaps are necessary on LE
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; The value of 1 is stored in the TOC.
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; No swaps are necessary when using P8 Vector instructions on LE
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define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
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%tmp = add <1 x i128> %a, <i128 1>
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ret <1 x i128> %tmp
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; FIXME: Seems a 128-bit literal is materialized by loading from the TOC. There
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; should be a better way of doing this.
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; CHECK-LE-LABEL: @v1i128_increment_by_one
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; CHECK-LE: xxswapd [[PARAM1:[0-9]+]], 34
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; CHECK-LE: stxvd2x [[PARAM1]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: lxvd2x [[RESULT:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: xxswapd 34, [[RESULT]]
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; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: xxswapd 35, [[VAL]]
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; CHECK-LE: vadduqm 2, 2, 3
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @v1i128_increment_by_one
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; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 34
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; CHECK-BE: stxvd2x 34, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE: lxvd2x 34, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd
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; CHECK-BE: vadduqm 2, 2, 3
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; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @v1i128_increment_by_one
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: stxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: lvx [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: lxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: vadduqm 2, 2, [[VAL]]
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; CHECK-NOVSX: blr
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}
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; VSX:
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; %a is passed in register 34
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; %b is passed in register 35
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; On LE, ensure the contents of 34 and 35 are swapped before being used
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; Similarly, on LE ensure the results are swapped before being returned in
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; register 34
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; No swaps are necessary when using P8 Vector instructions on LE
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; VMX (no VSX):
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; %a is passewd in register 2
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; %b is passed in register 3
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@@ -62,30 +62,20 @@ define <1 x i128> @v1i128_increment_by_val(<1 x i128> %a, <1 x i128> %b) nounwin
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ret <1 x i128> %tmp
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; CHECK-LE-LABEL: @v1i128_increment_by_val
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; CHECK-LE-DAG: xxswapd [[PARAM1:[0-9]+]], 34
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; CHECK-LE-DAG: xxswapd [[PARAM2:[0-9]+]], 35
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; CHECK-LE-DAG: stxvd2x [[PARAM1]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE-DAG: stxvd2x [[PARAM2]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: lxvd2x [[RESULT:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: xxswapd 34, [[RESULT]]
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; CHECK-LE-NOT: xxswapd
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; CHECK-LE: adduqm 2, 2, 3
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @v1i128_increment_by_val
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; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 34
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; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 35
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; CHECK-BE-DAG: stxvd2x 34, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-DAG: stxvd2x 35, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE: lxvd2x [[RESULT:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd 34, [[RESULT]]
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; CHECK-BE: adduqm 2, 2, 3
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @v1i128_increment_by_val
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-DAG: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-DAG: stvx 3, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: lvx [[RESULT:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd 34, [[RESULT]]
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; CHECK-NOVSX: adduqm 2, 2, 3
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; CHECK-NOVSX: blr
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}
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130
test/CodeGen/PowerPC/vec_add_sub_quadword.ll
Normal file
130
test/CodeGen/PowerPC/vec_add_sub_quadword.ll
Normal file
@@ -0,0 +1,130 @@
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; Check VMX 128-bit integer operations
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;
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {
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%result = add <1 x i128> %x, %y
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ret <1 x i128> %result
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; CHECK-LABEL: @test_add
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; CHECK: vadduqm 2, 2, 3
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}
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define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
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%result = add <1 x i128> %x, <i128 1>
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ret <1 x i128> %result
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; CHECK-LABEL: @increment_by_one
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; CHECK vadduqm 2, 2, 3
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}
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define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
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%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
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%tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
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%result = add <1 x i128> %x, %tmpvec2
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ret <1 x i128> %result
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; CHECK-LABEL: @increment_by_val
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; CHECK: vadduqm 2, 2, 3
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}
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define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind {
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%result = sub <1 x i128> %x, %y
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ret <1 x i128> %result
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; CHECK-LABEL: @test_sub
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; CHECK: vsubuqm 2, 2, 3
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}
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define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
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%result = sub <1 x i128> %x, <i128 1>
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ret <1 x i128> %result
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; CHECK-LABEL: @decrement_by_one
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; CHECK vsubuqm 2, 2, 3
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}
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define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
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%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
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%tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
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%result = sub <1 x i128> %x, %tmpvec2
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ret <1 x i128> %result
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; CHECK-LABEL: @decrement_by_val
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; CHECK vsubuqm 2, 2, 3
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}
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declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
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<1 x i128> %y) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
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<1 x i128> %y) nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind readnone
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define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z)
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ret <1 x i128> %tmp
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; CHECK-LABEL: @test_vaddeuqm
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; CHECK: vaddeuqm 2, 2, 3, 4
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}
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define <1 x i128> @test_vaddcuq(<1 x i128> %x,
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<1 x i128> %y) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
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<1 x i128> %y)
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ret <1 x i128> %tmp
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; CHECK-LABEL: @test_vaddcuq
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; CHECK: vaddcuq 2, 2, 3
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}
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define <1 x i128> @test_vaddecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z)
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ret <1 x i128> %tmp
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; CHECK-LABEL: @test_vaddecuq
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; CHECK: vaddecuq 2, 2, 3, 4
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}
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define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z)
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ret <1 x i128> %tmp
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; CHECK-LABEL: test_vsubeuqm
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; CHECK: vsubeuqm 2, 2, 3, 4
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}
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define <1 x i128> @test_vsubcuq(<1 x i128> %x,
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<1 x i128> %y) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
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<1 x i128> %y)
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ret <1 x i128> %tmp
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; CHECK-LABEL: test_vsubcuq
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; CHECK: vsubcuq 2, 2, 3
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}
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define <1 x i128> @test_vsubecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z) nounwind {
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
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<1 x i128> %y,
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<1 x i128> %z)
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ret <1 x i128> %tmp
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; CHECK-LABEL: test_vsubecuq
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; CHECK: vsubecuq 2, 2, 3, 4
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}
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