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Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sylvestre Ledru
2012-09-27 10:14:43 +00:00
parent 7e2c793a2b
commit 94c22716d6
84 changed files with 295 additions and 295 deletions
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6
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -5316,7 +5316,7 @@ validateInstruction(MCInst &Inst,
// instruction. We'll make the transformation in processInstruction()
// if necessary.
//
// Thumb LDM instructions are writeback if the base register is not
// Thumb LDM instructions are writeback iff the base register is not
// in the register list.
unsigned Rn = Inst.getOperand(0).getReg();
bool hasWritebackToken =
@@ -7023,7 +7023,7 @@ processInstruction(MCInst &Inst,
Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
break;
case ARM::tADDi8:
// If the immediate is in the range 0-7, we want tADDi3 if Rd was
// If the immediate is in the range 0-7, we want tADDi3 iff Rd was
// explicitly specified. From the ARM ARM: "Encoding T1 is preferred
// to encoding T2 if <Rd> is specified and encoding T2 is preferred
// to encoding T1 if <Rd> is omitted."
@@ -7033,7 +7033,7 @@ processInstruction(MCInst &Inst,
}
break;
case ARM::tSUBi8:
// If the immediate is in the range 0-7, we want tADDi3 if Rd was
// If the immediate is in the range 0-7, we want tADDi3 iff Rd was
// explicitly specified. From the ARM ARM: "Encoding T1 is preferred
// to encoding T2 if <Rd> is specified and encoding T2 is preferred
// to encoding T1 if <Rd> is omitted."